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Commit Graph

92330 Commits

Author SHA1 Message Date
Rafael Espindola
d23482285b Revert r182937 and r182877.
r182877 broke MCJIT tests on ARM and r182937 was working around another failure
by r182877.

This should make the ARM bots green.

llvm-svn: 182960
2013-05-30 20:37:52 +00:00
Rafael Espindola
bd67fd9669 Remove unused member.
llvm-svn: 182958
2013-05-30 20:19:35 +00:00
Eric Christopher
a16a93b865 Fix a couple of typos and 80-col.
llvm-svn: 182954
2013-05-30 18:59:11 +00:00
Bill Wendling
eaa4716121 Use the const_cast only where necessary.
llvm-svn: 182950
2013-05-30 18:52:57 +00:00
Ahmed Bougacha
e848455425 MCObjectSymbolizer: Switch from IntervalMap to sorted vector, following r182625.
This removes the need for the missing SectionRef operator< workaround, and fixes
an IntervalMap assert about alignment on MSVC.

llvm-svn: 182949
2013-05-30 18:18:36 +00:00
Michael Gottesman
2adb2144bb Implement IEEE-754R 2008 nextUp/nextDown functions in the guise of the function APFloat::next(bool nextDown).
rdar://13852078

llvm-svn: 182945
2013-05-30 18:07:13 +00:00
Paul Redmond
a9ddf6778b Fix warning and resulting formatting issue.
llvm-svn: 182939
2013-05-30 17:24:32 +00:00
Paul Redmond
029788a60b Revise llvm.vectorizer.width documentation
- clarify that vectorizer.width only applies if the vectorizer decides to
  vectorize.

llvm-svn: 182938
2013-05-30 17:22:46 +00:00
Rafael Espindola
ffa6fc3e48 Don't use fast isel on this test.
This fixes the test on ARM. Looks like it was broken by r182877. Not
sure if this is a bug on fast isel on ARM, but this should help fix
the ARM bots.

llvm-svn: 182937
2013-05-30 16:29:28 +00:00
Benjamin Kramer
f41318934e Force a triple so we don't get bitten by windows' different regalloc.
llvm-svn: 182935
2013-05-30 15:39:35 +00:00
Benjamin Kramer
8b559051e4 Force fragile test to the atom scheduler model.
The pattern the test originally checked for doesn't occur on other -mcpu
settings. On atom it's still there though slightly differently scheduled.

llvm-svn: 182933
2013-05-30 15:22:28 +00:00
Ashok Thirumurthi
8fc903dc03 Added a sub-project status update section to the release notes with details
on the LLDB 3.3 release.

Reviewed by: Greg Clayton and Bill Wendling

llvm-svn: 182931
2013-05-30 14:23:07 +00:00
Tim Northover
2b261b4ac3 X86: allow registers 8-15 in test
This test was failing on some hosts when an unexpected register was used for a
variable. This just extends the regexp to allow the new x86-64 registers.

llvm-svn: 182929
2013-05-30 13:56:32 +00:00
Tim Northover
aa5932cde5 X86: use sub-register sequences for MOV*r0 operations
Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions,
it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg")
and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is
smaller and partial register updates can sometimes be avoided.

Until recently, this sequence was a barrier to rematerialization though. That
should now be fixed so it's an appropriate time to make the change.

llvm-svn: 182928
2013-05-30 13:19:42 +00:00
Sergey Matveev
702cff7843 Fix incorrect parameter name in LIT docs.
llvm-svn: 182926
2013-05-30 12:37:52 +00:00
Tim Northover
9b176593cd Fix rematerialization into physical registers.
r182872 introduced a bug in how the register-coalescer's rematerialization
handled defining a physical register. It relied on the output of the
coalescer's setRegisters method to determine whether the replacement
instruction needed an implicit-def. However, this value isn't necessarily the
same as the CopyMI's actual destination register which is what the rest of the
basic-block expects us to be defining.

The commit changes the rematerializer to use the actual register attached to
CopyMI in its decision.

This will be tested soon by an X86 patch which moves everything to using
MOV32r0 instead of other sizes.

llvm-svn: 182925
2013-05-30 12:30:50 +00:00
Justin Holewinski
099d52887f [NVPTX] Fix case where a sext load of an i1 type may produce an
ld.u1 instead of an ld.u8.

llvm-svn: 182924
2013-05-30 12:22:39 +00:00
Tim Northover
4a589eb424 X86: change zext moves to use sub-register infrastructure.
32-bit writes on amd64 zero out the high bits of the corresponding 64-bit
register. LLVM makes use of this for zero-extension, but until now relied on
custom MCLowering and other code to fixup instructions. Now we have proper
handling of sub-registers, this can be done by creating SUBREG_TO_REG
instructions at selection-time.

Should be no change in functionality.

llvm-svn: 182921
2013-05-30 10:43:18 +00:00
Richard Sandiford
b7ab6fd782 [SystemZ] Enable unaligned accesses
The code to distinguish between unaligned and aligned addresses was
already there, so this is mostly just a switch-on-and-test process.

llvm-svn: 182920
2013-05-30 09:45:42 +00:00
Evgeniy Stepanov
49b05aa055 Revert r182909.
PR/16177

llvm-svn: 182919
2013-05-30 09:40:17 +00:00
Daniel Jasper
3fb2fd6c69 Fix warning on varialbe unused in opt builds.
llvm-svn: 182914
2013-05-30 07:01:43 +00:00
Galina Kistanova
1769d5a71b Fixed bug when tests in executable partially used absolute paths.
llvm-svn: 182910
2013-05-30 04:56:28 +00:00
Nick Lewycky
f69757c153 Swizzle vector inputs if it helps us eliminate shuffles.
llvm-svn: 182909
2013-05-30 04:33:38 +00:00
Rafael Espindola
5b34d5a3c7 Change how we iterate over relocations on ELF.
For COFF and MachO, sections semantically have relocations that apply to them.
That is not the case on ELF.

In relocatable objects (.o), a section with relocations in ELF has offsets to
another section where the relocations should be applied.

In dynamic objects and executables, relocations don't have an offset, they have
a virtual address. The section sh_info may or may not point to another section,
but that is not actually used for resolving the relocations.

This patch exposes that in the ObjectFile API. It has the following advantages:

* Most (all?) clients can handle this more efficiently. They will normally walk
all relocations, so doing an effort to iterate in a particular order doesn't
save time.

* llvm-readobj now prints relocations in the same way the native readelf does.

* probably most important, relocations that don't point to any section are now
visible. This is the case of relocations in the rela.dyn section. See the
updated relocation-executable.test for example.

llvm-svn: 182908
2013-05-30 03:05:14 +00:00
Eric Christopher
b4fed0cbed Rename variable to be more descriptive.
llvm-svn: 182903
2013-05-30 00:43:35 +00:00
Eric Christopher
e97cfa888f Formatting.
llvm-svn: 182902
2013-05-30 00:43:32 +00:00
Eric Christopher
7112ce79dc Reformat comments here.
llvm-svn: 182901
2013-05-30 00:43:30 +00:00
Eric Christopher
30048ba007 Add a comment and some tests including the NULL byte.
llvm-svn: 182900
2013-05-30 00:43:26 +00:00
Bill Wendling
cab3fa1f1c This testcase tests command line attributes which we don't yet support.
In fact, we're probably going to support these flags in completely different
ways. So this test is no longer valid.

llvm-svn: 182899
2013-05-30 00:32:04 +00:00
Rafael Espindola
ecf5cbb5aa Remove dead return.
llvm-svn: 182898
2013-05-30 00:29:46 +00:00
Michael Gottesman
bff1b48095 Added a unittest for APFloat::getSmallestNormalized.
llvm-svn: 182897
2013-05-30 00:18:47 +00:00
Michael Gottesman
09f3ab01b8 Added code to the unittest for APFloat::getSmallest to double check that we consider the result to be denormal.
I additionally changed certain checks to use EXPECT_FALSE instead of a boolean
complement with EXPECT_TRUE.

llvm-svn: 182896
2013-05-30 00:18:44 +00:00
Michael Gottesman
7fceea7dae Add a unittest for APFloat::getSmallest.
llvm-svn: 182894
2013-05-29 23:58:29 +00:00
Andrew Trick
aec414c298 Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.

Patch by Xiaoyi Guo!

This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.

llvm-svn: 182885
2013-05-29 22:03:55 +00:00
Ahmed Bougacha
6b9555bed9 X86: Fix Defs/Uses for insts that imp-def/imp-use both an A-register and EFLAGS.
This corrects a problem where x86 instructions that implicitly define/use both
an A-register (RAX, EAX, ..) and EFLAGS were declared as only defining/using
EFLAGS, because the outer "let Defs/Uses = [EFLAGS]" in the various multiclasses
overrides the "let Defs/Uses = [areg]" in BinOpAI.

The instructions deriving from BinOpAI were moved out of the "let Defs", and a
BinOpAI_FF class was created, for instructions that implicitly define and use
EFLAGS and the A-register (SBC, ADC).

llvm-svn: 182883
2013-05-29 21:13:57 +00:00
Chad Rosier
803e8d6083 Don't assume the registers will be enumerated sequentially.
llvm-svn: 182879
2013-05-29 20:42:21 +00:00
Arnaud A. de Grandmaison
6381fe608d Add colored diagnostics when building LLVM with cmake + ninja + clang
When invoked from Ninja, clang does not detect that it can use colors : see https://github.com/martine/ninja/issues/174

llvm-svn: 182878
2013-05-29 20:41:35 +00:00
JF Bastien
235d8c9117 Enable FastISel on ARM for Linux and NaCl
FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of test-suite on A15 hardware with --optimize-option=-O0 and
all the tests pass.

llvm-svn: 182877
2013-05-29 20:38:10 +00:00
Bill Wendling
e5fb3dbcbb Don't reach into the middle of TargetMachine and cache one of its ivars.
Not only does this break encapsulation, it's gross.

llvm-svn: 182876
2013-05-29 20:37:19 +00:00
Tim Northover
db2d7a34b2 Teach ReMaterialization to be more cunning about subregisters
This allows rematerialization during register coalescing to handle
more cases involving operations like SUBREG_TO_REG which might need to
be rematerialized using sub-register indices.

For example, code like:
    v1(GPR64):sub_32 = MOVZ something
    v2(GPR64) = COPY v1(GPR64)
should be convertable to:
    v2(GPR64):sub_32 = MOVZ something

but previously we just gave up in places like this

llvm-svn: 182872
2013-05-29 19:32:06 +00:00
Adrian Prantl
b6dada0e6e Simplify logic by using the appropriate functions.
llvm-svn: 182869
2013-05-29 17:33:31 +00:00
Manman Ren
7ef1e78101 LTO+Debug Info: revert r182791.
Since the testing case uses ref_addr, which requires version 3+ to work,
we will solve the dwarf version issue first.

This patch also causes failures in one of the bots. I will update the patch
accordingly in my next attempt.

rdar://13926659

llvm-svn: 182867
2013-05-29 17:16:59 +00:00
JF Bastien
1b5e07e947 Tidy some register classes for ARM and Thumb
Tidy up three places where the register class for ARM and Thumb wasn't
restrictive enough:
 - No PC dest for reg-reg add/orr/sub.
 - No PC dest for shifts.
 - No PC or SP for Thumb2 reg-imm add.

I encountered this while combining FastISel with
-verify-machineinstrs. These instructions defined registers whose
classes weren't restrictive enough, and the uses failed
verification. They're also undefined in the ISA, or would produce code
that FastISel wouldn't want. This doesn't fix the register class
narrowing issue (where uses should restrict definitions), and isn't
thorough, but it's a small step in the right direction.

llvm-svn: 182863
2013-05-29 15:45:47 +00:00
NAKAMURA Takumi
6eb30bda4d SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. [-Wunused-function]
llvm-svn: 182850
2013-05-29 12:10:42 +00:00
Richard Sandiford
b70371b744 [SystemZ] Two tests missing from previous commit
llvm-svn: 182847
2013-05-29 11:59:26 +00:00
Richard Sandiford
b62e20c071 [SystemZ] Immediate compare-and-branch support
This patch adds support for the CIJ and CGIJ instructions.

llvm-svn: 182846
2013-05-29 11:58:52 +00:00
Benjamin Kramer
c544c1401e Move test that depends on the X86 backend into the right subdirectory.
llvm-svn: 182834
2013-05-29 08:40:49 +00:00
Patrik Hagglund
5402d55791 Temporary fix to get rid of gcc warning.
llvm-svn: 182832
2013-05-29 07:32:08 +00:00
Evgeniy Stepanov
2371db6322 Allow overriding the location of C/C++ compilers in Android CMake build.
Patch by Greg Fitzgerald.

llvm-svn: 182831
2013-05-29 07:23:20 +00:00
Venkatraman Govindaraju
cb40ce1f29 [Sparc] Add support for leaf functions in sparc backend.
llvm-svn: 182822
2013-05-29 04:46:31 +00:00