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3920 Commits

Author SHA1 Message Date
Evan Cheng
70879e8dae - If a def is dead, do not spill it. 
- If the defs of a spilled rematerializable MI are dead after the spill store is deleted, delete
  the def MI as well.

llvm-svn: 41086
 2007-08-14 23:25:37 +00:00
Evan Cheng
f901915207 Fix for PR1596: AdjustCopiesBackFrom() should conservatively check if any of its sub-registers may overlap with the interval of the copy that's being coalesced. 
llvm-svn: 41084
 2007-08-14 23:19:28 +00:00
Evan Cheng
0fbe2a0ec4 If a MI's def is remat as well as spilled, and the store is later deemed dead, mark the def operand as isDead. 
llvm-svn: 41083
 2007-08-14 20:23:13 +00:00
Evan Cheng
de24ad8897 If a spilled value is being reused and the use is a kill, that means there are 
no more uses within the MBB and the spilled value isn't live out of the MBB.
Then it's safe to delete the spill store.

llvm-svn: 41069
 2007-08-14 09:11:18 +00:00
Evan Cheng
886c1fe427 If a rematerializable def is not deleted, i.e. it is also spilled, check if the 
spilled value is available for reuse.

llvm-svn: 41067
 2007-08-14 05:42:54 +00:00
Evan Cheng
5b64e19e06 Kill info update bugs. 
llvm-svn: 41064
 2007-08-14 01:56:58 +00:00
Evan Cheng
215f802b75 Re-implement trivial rematerialization. This allows def MIs whose live intervals that are coalesced to be rematerialized. 
llvm-svn: 41060
 2007-08-13 23:45:17 +00:00
Evan Cheng
54b799dc76 Kill info update bugs. 
llvm-svn: 41043
 2007-08-13 07:12:23 +00:00
Evan Cheng
3b211635e8 No need to remove dead range from soon-to-be-dead live interval. Its val# may be out of whack. 
llvm-svn: 41024
 2007-08-12 01:26:19 +00:00
Evan Cheng
8968affb6d Code to maintain kill information during register coalescing. 
llvm-svn: 41016
 2007-08-11 00:59:19 +00:00
Christopher Lamb
e0c9bd8d2e Move isSubRegOf into MRegisterInfo. Fix a missed move elimination in LowerSubregs and add more debugging output there. 
llvm-svn: 41005
 2007-08-10 21:11:55 +00:00
Dan Gohman
f18e94535f Fix EXTRACT_ELEMENT, EXTRACT_SUBVECTOR, and EXTRACT_VECTOR_ELT to 
use an intptr ValueType instead of i32 for the index operand in
getCopyToParts.

llvm-svn: 40987
 2007-08-10 14:59:38 +00:00
Rafael Espindola
b20b9e985a propagate struct size and alignment of byval arguments to the DAG 
llvm-svn: 40986
 2007-08-10 14:44:42 +00:00
Chris Lattner
202e7f84e9 unbreak the build 
llvm-svn: 40976
 2007-08-09 23:55:17 +00:00
Evan Cheng
0293fe7483 Bug fix. ~1U marks the val# dead. 
llvm-svn: 40975
 2007-08-09 23:14:39 +00:00
Dale Johannesen
a1340d5916 Update per review comments. 
llvm-svn: 40965
 2007-08-09 17:27:48 +00:00
Dale Johannesen
79551baaad long double 9 of N. This finishes up the X86-32 bits 
(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958
 2007-08-09 01:04:01 +00:00
Scott Michel
86052f49c0 If a target really needs to custom lower constants, it should be allowed 
to do so.

llvm-svn: 40955
 2007-08-08 23:23:31 +00:00
Evan Cheng
5227e36428 Adding kill info to val#. 
llvm-svn: 40925
 2007-08-08 07:03:29 +00:00
Evan Cheng
02e7fbd7c8 Clean up and bug fix. 
llvm-svn: 40921
 2007-08-08 05:56:18 +00:00
Evan Cheng
12d72cc1a0 - Each val# can have multiple kills. 
- Fix some minor bugs related to special markers on val# def. ~0U means
  undefined, ~1U means dead val#.

llvm-svn: 40916
 2007-08-08 03:00:28 +00:00
Evan Cheng
b4135e3825 Remove a dead assertion. 
llvm-svn: 40914
 2007-08-08 01:00:21 +00:00
Evan Cheng
0182b495fd - LiveInterval value#'s now have 3 components: def instruction #, 
kill instruction #, and source register number (iff the value# is defined by a
copy).
- Now def instruction # is set for every value#, not just for copy defined ones.
- Update some outdated code related inactive live ranges.
- Kill info not yet set. That's next patch.

llvm-svn: 40913
 2007-08-07 23:49:57 +00:00
David Greene
f0a40d3dc2 Add a missing forward declaration. 
llvm-svn: 40896
 2007-08-07 16:34:05 +00:00
Chris Lattner
a374edf4a6 Fix a regression compiling 2005-05-11-Popcount-ffs-fls with the CBE, 
introduced by chandler's patch.

llvm-svn: 40864
 2007-08-06 16:36:18 +00:00
Christopher Lamb
8875f43912 Implement review feedback. No functionality change. 
llvm-svn: 40863
 2007-08-06 16:33:56 +00:00
Reid Spencer
3e54e72ef1 Fix minor doxygen nits. 
llvm-svn: 40854
 2007-08-05 20:06:04 +00:00
Chris Lattner
bc90e7255f shorten this name 
llvm-svn: 40843
 2007-08-05 18:45:33 +00:00
Chandler Carruth
00e56b0e81 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. 
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807
 2007-08-04 01:51:18 +00:00
Dan Gohman
352de5aeb9 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Chris Lattner
9319dfc93a don't redefine a parameter 
llvm-svn: 40748
 2007-08-02 18:08:16 +00:00
Evan Cheng
a06b9cf09f Do not emit copies for physical register output if it's not used. 
llvm-svn: 40722
 2007-08-02 05:29:38 +00:00
Scott Michel
199544367f Style police: Expand the tabs to spaces! 
llvm-svn: 40712
 2007-08-02 02:22:46 +00:00
Evan Cheng
14bd520741 Instead of adding copyfromreg's to handle physical definitions. Now isel can 
simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)

Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)

And let scheduledag emit the move from X86::EAX to a virtual register.

llvm-svn: 40710
 2007-08-02 00:28:15 +00:00
Evan Cheng
d6d66f0cf4 Bugs: missing partial uses and redundant partial defs. 
llvm-svn: 40688
 2007-08-01 20:18:21 +00:00
Lauro Ramos Venancio
1ef30713de Expand unaligned loads/stores when the target doesn't support them. (PR1548) 
llvm-svn: 40682
 2007-08-01 19:34:21 +00:00
David Greene
f06a395bb9 New CallInst interface to address GLIBCXX_DEBUG errors caused by 
indexing an empty std::vector.

Updates to all clients.

llvm-svn: 40660
 2007-08-01 03:43:44 +00:00
Evan Cheng
8889a56947 simpleregistercoalescing -> regcoalescing. It's too long for me to handle. 
llvm-svn: 40654
 2007-07-31 22:37:44 +00:00
Scott Michel
c65b4c8eeb - Allow custom lowering for CTPOP, CTTZ, CTLZ. 
- Fixed an existing unexpanded tab.

llvm-svn: 40605
 2007-07-30 21:00:31 +00:00
Dan Gohman
375d541183 Fix a bug in getCopyFromParts turned up in the testcase for PR1132. 
llvm-svn: 40598
 2007-07-30 19:09:17 +00:00
Dan Gohman
555f611994 Print a space between the comment character and the basic block name, 
for prettiness.

llvm-svn: 40593
 2007-07-30 15:06:25 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Christopher Lamb
55a1e36013 Move subreg lowering pass to be right after regalloc, per feedback. 
llvm-svn: 40548
 2007-07-27 07:36:14 +00:00
Dan Gohman
249090568d Fix the alias analysis query in DAGCombiner to not add in two 
offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.

llvm-svn: 40534
 2007-07-26 16:14:06 +00:00
Christopher Lamb
258dab5389 Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions. 
llvm-svn: 40521
 2007-07-26 08:18:32 +00:00
Christopher Lamb
08bcd5c0f8 Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350 
llvm-svn: 40520
 2007-07-26 08:12:07 +00:00
Christopher Lamb
73c3cd47cc Add selection DAG nodes for subreg insert/extract. PR1350 
llvm-svn: 40516
 2007-07-26 07:34:40 +00:00
Christopher Lamb
cb63a77a51 Remove subreg index from MachineInstr's and also keep vregs as unsigned when adding operands. 
llvm-svn: 40514
 2007-07-26 07:00:46 +00:00
Christopher Lamb
b178ecbbc0 Fix infinite recursion for when extract_vector_elt is legal. Unfortunately no public targets use this code-path, so no test. 
llvm-svn: 40510
 2007-07-26 03:33:13 +00:00
Evan Cheng
4b747bb6a0 EmitAlignment() also emits optional fill value. 
llvm-svn: 40500
 2007-07-25 23:35:07 +00:00