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Commit Graph

66389 Commits

Author SHA1 Message Date
Duncan Sands
a7198342e7 If a function does a volatile load from a global constant, do not
consider it to be readonly.  In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment).  This fixes PR8279.

llvm-svn: 117783
2010-10-30 12:59:44 +00:00
Jim Grosbach
775afa274f Tidy up.
llvm-svn: 117782
2010-10-30 12:59:16 +00:00
Chris Lattner
ee8dea6453 Rename alignof -> alignOf to avoid irritating C++'0x compilers,
PR8423, patch by nobled.

llvm-svn: 117774
2010-10-30 05:14:01 +00:00
Chris Lattner
45c679522d stay out of the reserved namespace
llvm-svn: 117773
2010-10-30 04:57:14 +00:00
Chris Lattner
deabc3d7fa simplify this code.
llvm-svn: 117771
2010-10-30 04:35:59 +00:00
Chris Lattner
3a36dd4a0b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
llvm-svn: 117769
2010-10-30 04:09:10 +00:00
Jim Grosbach
298cac8db3 Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
llvm-svn: 117766
2010-10-30 01:40:16 +00:00
Jakob Stoklund Olesen
b3b1db4e67 Include MachineBasicBlock numbers in viewCFG() output.
llvm-svn: 117765
2010-10-30 01:26:19 +00:00
Jakob Stoklund Olesen
035667c0d6 Make sure copies are inserted after any exception handling labels at the top of
a basic block.

llvm-svn: 117764
2010-10-30 01:26:16 +00:00
Jakob Stoklund Olesen
0ab92619d0 Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is needed
elsewhere.

llvm-svn: 117763
2010-10-30 01:26:14 +00:00
Jakob Stoklund Olesen
b751dffc9f Disable more of physical register live intervals verification.
llvm-svn: 117762
2010-10-30 01:26:11 +00:00
Jakob Stoklund Olesen
4425035bfd Print out register class of spilled register.
llvm-svn: 117761
2010-10-30 01:26:09 +00:00
Bob Wilson
183c466006 Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756
2010-10-30 00:54:37 +00:00
Tobias Grosser
45db9e63fb Add polly support to the build system.
Update the cmake and autoconf build system to compile polly
as a shared library if it is checked out into tools/polly. In case
polly is not checked out, nothing changes.
This models the way clang can be added to llvm if checked out to tools/clang.

Also rebuild configure.

Patch contributed by ether.

llvm-svn: 117755
2010-10-30 00:54:26 +00:00
Jim Grosbach
996d1280bd Encode the register list operands for ARM mode LDM/STM instructions.
llvm-svn: 117753
2010-10-30 00:37:59 +00:00
Bill Wendling
b68e0d0ee3 Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.

llvm-svn: 117747
2010-10-29 23:50:21 +00:00
John Thompson
771289ca4a Mult-alt constraint incremental development step 3.
llvm-svn: 117746
2010-10-29 23:37:38 +00:00
Evan Cheng
d81c33d91e Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.
llvm-svn: 117745
2010-10-29 23:36:03 +00:00
Jim Grosbach
9a473e23b8 Remove hard tab characters.
llvm-svn: 117742
2010-10-29 23:23:15 +00:00
Jim Grosbach
7ca6ac347d 80 column fix.
llvm-svn: 117741
2010-10-29 23:21:57 +00:00
Jim Grosbach
038d376c59 trailing whitespace
llvm-svn: 117740
2010-10-29 23:21:03 +00:00
Jim Grosbach
7cf8dcc5bd s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
encoder functions.

llvm-svn: 117738
2010-10-29 23:19:55 +00:00
Evan Cheng
7695213793 Fix fpscr <-> GPR latency info.
llvm-svn: 117737
2010-10-29 23:16:55 +00:00
Rafael Espindola
0d9ac34ffa Be more strict on when we produce an undefined reference. In gas a file with
just

.type   foo,@object

will produce an undefined reference to foo. On the other hand, a file with
just

.weakref bar, foo

will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.

With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.

This is in preparation for a patch implementing .weakref.

llvm-svn: 117735
2010-10-29 23:09:31 +00:00
Dan Gohman
09a2a554e2 Apply a patch from Frits van Bommel to fix the CMake build.
llvm-svn: 117731
2010-10-29 22:36:50 +00:00
Bob Wilson
d84c4629c1 Clean up indentation and other whitespace.
llvm-svn: 117728
2010-10-29 22:20:45 +00:00
Bob Wilson
9297637759 Remove trailing whitespace.
llvm-svn: 117727
2010-10-29 22:20:43 +00:00
Jim Grosbach
91b6672682 trailing whitespace
llvm-svn: 117724
2010-10-29 22:13:48 +00:00
Bob Wilson
59dedc2629 Fix 80-column violation.
llvm-svn: 117722
2010-10-29 22:03:07 +00:00
Bob Wilson
d7f24e831f Change instcombine's getShuffleMask to represent undef with negative values.
This code had previously used 2*N, where N is the mask length, to represent
undef.  That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.

llvm-svn: 117721
2010-10-29 22:03:05 +00:00
Bob Wilson
d67dddb134 Remove DAG combiner patch to fold vector splats. Instcombiner does it now.
llvm-svn: 117720
2010-10-29 22:03:02 +00:00
Bob Wilson
996353fb5d Make instcombine a little more aggressive in combining vector shuffles.
Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks.  Radar 8597790.
Also fix some 80-column violations.

llvm-svn: 117719
2010-10-29 22:02:50 +00:00
Jim Grosbach
e811e91d02 add FIXME
llvm-svn: 117718
2010-10-29 21:56:51 +00:00
Jim Grosbach
fcfc42b7bb Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
2010-10-29 21:35:25 +00:00
Owen Anderson
14cf6bfa0f Update testcase since we're no longer doing the constant forwarding inline with correlated value propagation.
llvm-svn: 117712
2010-10-29 21:18:23 +00:00
Eric Christopher
bf7cf2a203 Handle comparison values we already have - this fixes the consumer-typeset
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
2010-10-29 21:08:19 +00:00
Owen Anderson
b41f027059 Give up on doing in-line instruction simplification during correlated value propagation. Instruction simplification
needs to be guaranteed never to be run on an unreachable block.  However, earlier block simplifications may have
changed the CFG to make block that were reachable when we began our iteration unreachable by the time we try to
simplify them. (Note that this also means that our depth-first iterators were potentially being invalidated).

This should not have a large impact on code quality, since later runs of instcombine should pick up these simplifications.
Fixes PR8506.

llvm-svn: 117709
2010-10-29 21:05:17 +00:00
Owen Anderson
ccbb8e7b65 Convert this test to .s form.
llvm-svn: 117708
2010-10-29 20:39:19 +00:00
Jim Grosbach
93fbda05ee ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
handle it in the asm lowering.

llvm-svn: 117707
2010-10-29 20:37:06 +00:00
Owen Anderson
7e3af87961 Convert this test to .s form.
llvm-svn: 117704
2010-10-29 20:23:45 +00:00
Jim Grosbach
52638aa1c8 Fix typo.
llvm-svn: 117703
2010-10-29 20:21:49 +00:00
Jim Grosbach
4ca61d9877 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
llvm-svn: 117702
2010-10-29 20:21:36 +00:00
Dan Gohman
adc29a454a not is testing for a normal exit with a non-zero value. It shouldn't
return success if the child process is killed with a signal.

llvm-svn: 117701
2010-10-29 20:20:29 +00:00
Owen Anderson
1b3d8432b1 Convert this test to .s form.
llvm-svn: 117699
2010-10-29 20:17:07 +00:00
Dan Gohman
85557399a1 Make ScalarEvolution::forgetLoop forget all contained loops too, because
they may have ValuesAtScopes map entries referencing their outer loops.
This fixes a user-after-free reported in PR8471.

llvm-svn: 117698
2010-10-29 20:16:10 +00:00
Owen Anderson
fc007fef16 Convert this test to .s form.
llvm-svn: 117696
2010-10-29 20:12:34 +00:00
Jim Grosbach
162e3345fb ARM mode LDREX*/STREX* binary encodings.
llvm-svn: 117695
2010-10-29 19:58:57 +00:00
Owen Anderson
2119e59322 Covert this test to .s form.
llvm-svn: 117694
2010-10-29 19:56:07 +00:00
Owen Anderson
b75ef99b0c Convert this test to .s form.
llvm-svn: 117693
2010-10-29 19:51:11 +00:00
Owen Anderson
9e3265d3da Convert this test to .s form.
llvm-svn: 117690
2010-10-29 19:45:32 +00:00