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Author SHA1 Message Date
Chris Lattner
d57d9e862d eliminate the old InstFormatName which is always "AsmString", 
simplify CodeGenInstruction. No functionality change.

llvm-svn: 117891
 2010-11-01 02:15:23 +00:00
Chris Lattner
a8d1d91f41 all predicates on an MnemonicAlias must be AssemblerPredicates. 
llvm-svn: 117890
 2010-11-01 02:09:21 +00:00
Chris Lattner
22f9108208 change the singleton register handling code to be based on Record*'s 
instead of strings, simplifying it.

llvm-svn: 117889
 2010-11-01 01:47:07 +00:00
Chris Lattner
359e5c93e8 Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of 
argument passing.  Consolidate all SingletonRegister detection
and handling into a new 
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about.  No change in generated .inc files.

llvm-svn: 117888
 2010-11-01 01:37:30 +00:00
Chris Lattner
0a33c519da move FlattenVariants out of AsmMatcherEmitter into a shared 
CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.

llvm-svn: 117886
 2010-11-01 01:07:14 +00:00
Chris Lattner
466a3f6029 add a FIXME, $lane in ARM is an issue that needs to be resolved before 
this can start rejecting instructions.

llvm-svn: 117885
 2010-11-01 00:51:32 +00:00
Chris Lattner
9da275f86b reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Chandler Carruth
4d8fbad207 Add a specialization for 'long', a hole in the set of fundamental 
specializations provided here. This is a little annoying because its size
changes from platform to platform. If possible, I may follow up with a patch
that uses standard constants to simplify much of this, but assuming for now
that was avoided for a reason.

llvm-svn: 117880
 2010-10-31 22:57:03 +00:00
Eric Christopher
7295ed492c Revert r117876 for now, it's causing more testsuite failures. 
llvm-svn: 117879
 2010-10-31 22:42:55 +00:00
Bill Wendling
13936421e6 Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is what 
looks like is happening:

Without the peephole optimizer:
  (1)   sub     r6, r6, #32
        orr     r12, r12, lr, lsl r9
        orr     r2, r2, r3, lsl r10
  (x)   cmp     r6, #0
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (2)   sub     r8, r8, #32
  (a)   movge   r12, lr, lsr r6
  (y)   cmp     r8, #0
LPC2_10:
        ldr     lr, [pc, r10]
  (b)   movge   r2, r3, lsr r8

With the peephole optimizer:
        ldr     r9, LCPI2_10
        ldr     r10, LCPI2_11
  (1*)  subs    r6, r6, #32
  (2*)  subs    r8, r8, #32
  (a*)  movge   r12, lr, lsr r6
  (b*)  movge   r2, r3, lsr r8

(1) is used by (x) for the conditional move at (a). (2) is used by (y) for the
conditional move at (b). After the peephole optimizer, these the flags resulting
from (1*) are ignored and only the flags from (2*) are considered for both
conditional moves.

llvm-svn: 117876
 2010-10-31 22:07:12 +00:00
Nicolas Geoffray
6889997474 Attach a GCModuleInfo to a MachineFunction. 
llvm-svn: 117867
 2010-10-31 20:38:38 +00:00
Chris Lattner
4e42d39402 fix a crash on: 
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {

we now get:

X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
                                                   ^

llvm-svn: 117863
 2010-10-31 19:27:15 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner
5d088218e5 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner
01acd65875 reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).

llvm-svn: 117860
 2010-10-31 19:10:56 +00:00
Chris Lattner
8132a182e7 revert r117858 while I check out a failure I missed. 
llvm-svn: 117859
 2010-10-31 19:05:32 +00:00
Chris Lattner
70b05a5b88 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Chris Lattner
8aaac91ca4 sketch out the planned instruction alias mechanism, add some comments about 
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
 2010-10-31 18:43:46 +00:00
Duncan Sands
92f33ea784 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
 2010-10-31 13:21:44 +00:00
Duncan Sands
0f49c49476 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
 2010-10-31 13:02:38 +00:00
Duncan Sands
812f6878ea Explain the return value of CCAssignFn. 
llvm-svn: 117854
 2010-10-31 10:29:14 +00:00
Rafael Espindola
660b7f5c4a Add support for files with more than 65280 sections. No testcase since 
it would be a bit too big :-)

llvm-svn: 117849
 2010-10-31 00:16:26 +00:00
Eric Christopher
e012ee8db9 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Benjamin Kramer
63031c7df3 Validate HTML. 
llvm-svn: 117847
 2010-10-30 21:07:28 +00:00
Chris Lattner
2624c9ccb0 add missing tag 
llvm-svn: 117846
 2010-10-30 20:21:00 +00:00
Chris Lattner
19ccfc3d63 have GetAliasRequiredFeatures get its features from 
AsmMatcherInfo so we don't have two places that know the
feature -> enum mapping.  No functionality change.

llvm-svn: 117845
 2010-10-30 20:15:02 +00:00
Chris Lattner
17980631fb simplify code that creates SubtargetFeatureInfo, ensuring that features 
that are only used by MnemonicAliases will be found.

llvm-svn: 117844
 2010-10-30 20:07:57 +00:00
Chris Lattner
d4ea8ee6f2 fix a fixme in stringmatcher, having it generate nice looking code if the 
'tomatch' code contains \n's.

llvm-svn: 117843
 2010-10-30 19:57:17 +00:00
Chris Lattner
aace31ce48 fix typos and some serious bugs in feature handling (but not for 
cases that are currently exercised).  Thanks to Frits van Bommel for
the great review!

llvm-svn: 117840
 2010-10-30 19:47:49 +00:00
Chris Lattner
49227ad505 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner
15e92ddd01 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner
cce5ecf2cc fix build problem 
llvm-svn: 117828
 2010-10-30 18:57:07 +00:00
Chris Lattner
aaa72fa2af diagnose targets that define two alises with the same 'from' mnemonic 
with a useful error message instead of having tblgen explode with an 
assert.

llvm-svn: 117827
 2010-10-30 18:56:12 +00:00
Chris Lattner
3daf6d69dc emit the mnemonic aliases in their own helper function instead of 
inline into MatchInstructionImpl.

llvm-svn: 117826
 2010-10-30 18:48:18 +00:00
Chris Lattner
441672d7cb really zap alias. 
llvm-svn: 117824
 2010-10-30 18:23:25 +00:00
Chris Lattner
ba9271be5b move fcompi alias to .td file and zap some useless code. 
llvm-svn: 117823
 2010-10-30 18:22:53 +00:00
Chris Lattner
1b3b2e113f move rep aliases to td file 
llvm-svn: 117822
 2010-10-30 18:17:33 +00:00
Chris Lattner
49f977366f move sal aliases to .td file. 
llvm-svn: 117821
 2010-10-30 18:14:54 +00:00
Chris Lattner
54892b4d8d fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner
38179edecd move a bunch more aliases from .cpp -> .td file. 
llvm-svn: 117819
 2010-10-30 18:07:17 +00:00
Chris Lattner
ac7f4957b1 move cmov aliases to .td file. 
llvm-svn: 117818
 2010-10-30 17:56:50 +00:00
Chris Lattner
acec7b7d46 move setcc and jcc aliases from .cpp to .td 
llvm-svn: 117817
 2010-10-30 17:51:45 +00:00
Chris Lattner
e90ff8dcb6 move some code. 
llvm-svn: 117816
 2010-10-30 17:38:55 +00:00
Chris Lattner
7c61e4bca2 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Chris Lattner
f0bb464017 add a test for the ud2a alias. 
llvm-svn: 117803
 2010-10-30 17:01:25 +00:00
Duncan Sands
a8d9d6c6e3 Now that the MallocInst no longer exists, this workaround for 
it claiming not to have side-effects is no longer needed.

llvm-svn: 117789
 2010-10-30 16:12:16 +00:00
Jim Grosbach
c160d7a3ae Allow specifying a CPU to llvm-mc, so that we can properly set up subtarget 
feature lists for instruction pattern predicates.

llvm-svn: 117788
 2010-10-30 15:57:50 +00:00
Jim Grosbach
b6c76a2662 Add FIXME. 
llvm-svn: 117787
 2010-10-30 14:54:23 +00:00
Jim Grosbach
951667ac39 Clean up comments. 
llvm-svn: 117785
 2010-10-30 13:48:28 +00:00
Jim Grosbach
ddf6d9ec2f 80 columns. 
llvm-svn: 117784
 2010-10-30 13:46:39 +00:00