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4351 Commits

Author SHA1 Message Date
Jim Grosbach
d788f9b580 back out 104862/104869. Can reuse stacksave after all. Very cool. 
llvm-svn: 104897
 2010-05-27 23:11:57 +00:00
Jim Grosbach
0ff473d68a hook ISD::STACKADDR to an intrinsic 
llvm-svn: 104869
 2010-05-27 18:52:11 +00:00
Bill Wendling
a874b6d45a Add FIXME comment to remove this. 
llvm-svn: 104749
 2010-05-26 21:53:50 +00:00
Bill Wendling
49b19ff2c3 Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of 
usual suspects that could "return twice".

llvm-svn: 104737
 2010-05-26 20:39:00 +00:00
Jim Grosbach
bb4860d2a2 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.

llvm-svn: 104734
 2010-05-26 20:22:18 +00:00
Devang Patel
2ea3f77515 Update debug info when live-in reg is copied into a vreg. 
llvm-svn: 104732
 2010-05-26 20:18:50 +00:00
Bill Wendling
fbe85886bb Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by 
more than just the stack slot coloring algorithm.

llvm-svn: 104722
 2010-05-26 19:46:12 +00:00
Dan Gohman
616845c384 Eliminate the use of PriorityQueue and just use a std::vector, 
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.

llvm-svn: 104718
 2010-05-26 18:52:00 +00:00
Dan Gohman
a4a49b2108 Delete an unused function. 
llvm-svn: 104716
 2010-05-26 18:34:12 +00:00
Eric Christopher
13ac28ede3 Temporarily revert r104655 as it's breaking the bots. 
llvm-svn: 104664
 2010-05-26 01:59:55 +00:00
Dan Gohman
59cddd1327 Change push_all to a non-virtual function and implement it in the 
base class, since all the implementations are the same.

llvm-svn: 104659
 2010-05-26 01:10:55 +00:00
Dan Gohman
ff4bf1aacf Trim #include. 
llvm-svn: 104657
 2010-05-26 00:55:59 +00:00
Bill Wendling
04fbdac5ac Dale and Evan suggested putting the "check for setjmp" much earlier in the 
machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655
 2010-05-26 00:32:40 +00:00
Dan Gohman
803cd02b11 Do one map lookup instead of two. 
llvm-svn: 104645
 2010-05-25 21:59:42 +00:00
Dale Johannesen
8fd73c1910 Fix another variant of PR 7191. Also add a testcase 
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624
 2010-05-25 18:47:23 +00:00
Dale Johannesen
42c91e9024 Fix PR 7191. I have been unable to create a .ll file that fails, sorry. 
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)

llvm-svn: 104619
 2010-05-25 17:50:03 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Bob Wilson
3994f42952 Clean up extra whitespace. 
llvm-svn: 104410
 2010-05-21 23:53:55 +00:00
Bob Wilson
586811b244 Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
 2010-05-21 21:05:32 +00:00
Evan Cheng
1faccbd51a Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid. 
llvm-svn: 104306
 2010-05-21 00:42:32 +00:00
Evan Cheng
b5de7de4ce Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
llvm-svn: 104293
 2010-05-20 23:26:43 +00:00
Evan Cheng
0d88ad2de1 Add a hybrid bottom up scheduler that reduce register usage while avoiding 
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216
 2010-05-20 06:13:19 +00:00
Bob Wilson
2dbe0d9886 Optimize away insertelement of an undef value. This shows up in 
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.

llvm-svn: 104185
 2010-05-19 23:42:58 +00:00
Evan Cheng
9fe8c861bf Code clean up. 
llvm-svn: 104173
 2010-05-19 22:42:23 +00:00
Evan Cheng
46e08acfa5 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
llvm-svn: 104147
 2010-05-19 20:19:50 +00:00
Bob Wilson
ae9655920b When expanding a vector_shuffle, the element type may not be legal and may 
need to be promoted.  The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion.  This fixes part of pr7167.

llvm-svn: 104141
 2010-05-19 18:48:32 +00:00
Evan Cheng
632cb17357 Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. 
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094
 2010-05-19 01:08:17 +00:00
Evan Cheng
e2980af336 Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
llvm-svn: 104060
 2010-05-18 21:31:17 +00:00
Evan Cheng
dae4e9e4bc Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices. 
llvm-svn: 104051
 2010-05-18 20:07:47 +00:00
Evan Cheng
9fc34e676d Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE. 
llvm-svn: 104050
 2010-05-18 20:03:28 +00:00
Evan Cheng
39b5115e93 FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). 
llvm-svn: 104004
 2010-05-18 00:03:40 +00:00
Bill Wendling
5a1c9f8d06 - Set the "HasCalls" flag after instruction selection is finished. 
- Change the logic DisableFramePointerElim() to check for the
  -disable-non-leaf-fp-elim before -disable-fp-elim.

llvm-svn: 103990
 2010-05-17 23:09:50 +00:00
Dale Johannesen
82dfdcdde7 Fix uint64->{float, double} conversion to do rounding correctly in 32-bit. 
The implementation in LegalizeIntegerTypes to handle this as 
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people.  Use this implementation only
when it is safe.  This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)

Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.

7885399, 5901940.  This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.

llvm-svn: 103883
 2010-05-15 18:51:12 +00:00
Dale Johannesen
d093363ea5 Improve assertion messages. 
llvm-svn: 103882
 2010-05-15 18:38:02 +00:00
Dan Gohman
4049434a04 Fast ISel trivially coalesces away no-op casts, so check for this when 
setting kill flags.

llvm-svn: 103832
 2010-05-14 22:53:18 +00:00
Dan Gohman
97d22ade75 Don't set kill flags for instructions which the scheduler has cloned. 
llvm-svn: 103827
 2010-05-14 22:01:14 +00:00
Bill Wendling
e346a38ed4 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.

llvm-svn: 103802
 2010-05-14 21:14:32 +00:00
Dale Johannesen
9f19b6a761 Implement a correct ui64->f32 conversion. The old 
one was subject to double rounding in extreme cases.

llvm-svn: 103744
 2010-05-13 23:50:42 +00:00
Dan Gohman
d7b4c5b82e An Instruction has a trivial kill only if its use is in the same 
basic block.

llvm-svn: 103725
 2010-05-13 19:19:32 +00:00
Dan Gohman
03e407ed83 Add initial kill flag support to FastISel. 
llvm-svn: 103529
 2010-05-11 23:54:07 +00:00
Dan Gohman
2ace137eb9 Don't set kill flags on uses of CopyFromReg nodes. InstrEmitter doesn't 
create separate virtual registers for CopyFromReg values, so uses of
them don't necessarily kill the value.

llvm-svn: 103519
 2010-05-11 21:59:14 +00:00
Duncan Sands
7d5e4152c3 I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.

llvm-svn: 103495
 2010-05-11 20:16:09 +00:00
Dan Gohman
ca2df906ae Trim #includes and forward declarations. 
llvm-svn: 103489
 2010-05-11 19:11:43 +00:00
Dan Gohman
fb6f4da0e0 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Douglas Gregor
2f2491405a Fixes for Microsoft Visual Studio 2010, from Steven Watanabe! 
llvm-svn: 103457
 2010-05-11 06:17:44 +00:00
Evan Cheng
de3482f4af Indentation. 
llvm-svn: 103441
 2010-05-10 23:08:19 +00:00
Evan Cheng
df350445c6 Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869. 
llvm-svn: 103419
 2010-05-10 19:03:57 +00:00
Duncan Sands
83c7bda62e Add an assertion to catch attempts to access off the end of the array. 
Based on a patch by Javier Martinez.

llvm-svn: 103391
 2010-05-10 04:54:28 +00:00
Dan Gohman
95040c18f4 SDDbgValues are apparently not being legalized. Fix a symptom of the problem, 
and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.

llvm-svn: 103310
 2010-05-07 22:19:08 +00:00
Devang Patel
3c2f4664fc Verify variable directly. 
llvm-svn: 103305
 2010-05-07 22:04:20 +00:00