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Commit Graph

3148 Commits

Author SHA1 Message Date
Bob Wilson
d79e684d1e Fix a minor bug in DAGCombiner's folding of SELECT. Folding "select C, 0, 1"
to "C ^ 1" is only valid when C is known to be either 0 or 1.  Most of the
similar foldings in this function only handle "i1" types, but this one appears
intentionally written to handle larger integer types.  If C has an integer
type larger than "i1", this needs to check if the high bits of a boolean
are known to be zero.  I also changed the comment to describe this folding as
"C ^ 1" instead of "~C", since that is what the code does and since the latter
would only be valid for "i1" types.  The good news is that most LLVM targets
use TargetLowering::ZeroOrOneBooleanContent so this change will not disable
the optimization; the bad news is that I've been unable to come up with a
testcase to demonstrate the problem.

I have also removed a "FIXME" comment for folding "select C, X, 0" to "C & X",
since the code looks correct to me.  It could be made more aggressive by not
limiting the type to "i1", but that would then require checking for
TargetLowering::ZeroOrNegativeOneBooleanContent.  Similar changes could be
done for the other SELECT foldings, but it was decided to be not worth the
trouble and complexity (see e.g., r44663).

llvm-svn: 62790
2009-01-22 22:05:48 +00:00
Dan Gohman
a6e5948fce Don't create ISD::FNEG nodes after legalize if they aren't legal.
Simplify x+0 to x in unsafe-fp-math mode. This avoids a bunch of
redundant work in many cases, because in unsafe-fp-math mode,
ISD::FADD with a constant is considered free to negate, so the
DAGCombiner often negates x+0 to -0-x thinking it's free, when
in reality the end result is -x, which is more expensive than x.

Also, combine x*0 to 0.

This fixes PR3374.

llvm-svn: 62789
2009-01-22 21:58:43 +00:00
Bob Wilson
186046e657 Add SelectionDAG::getNOT method to construct bitwise NOT operations,
corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.

llvm-svn: 62768
2009-01-22 17:39:32 +00:00
Evan Cheng
c971801ae1 Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.
llvm-svn: 62762
2009-01-22 09:10:11 +00:00
Chris Lattner
92f592ad8b fix a typo
llvm-svn: 62761
2009-01-22 07:21:55 +00:00
Dan Gohman
d021a20409 Simplify ReduceLoadWidth's logic: it doesn't need several different
special cases after producing the new reduced-width load, because the
new load already has the needed adjustments built into it. This fixes
several bugs due to the special cases, including PR3317.

llvm-svn: 62692
2009-01-21 15:17:51 +00:00
Duncan Sands
392dc77fc6 Cleanup whitespace and comments, and tweak some
prototypes, in operand type legalization.  No
functionality change.

llvm-svn: 62680
2009-01-21 09:00:29 +00:00
Scott Michel
c80e71ac35 CellSPU:
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.

llvm-svn: 62664
2009-01-21 04:58:48 +00:00
Sanjiv Gupta
074553c4fb Allow targets to legalize operations (with illegal operands) that produces multiple values. For example, a load with an illegal operand (a load produces two values, a value and chain).
llvm-svn: 62663
2009-01-21 04:48:39 +00:00
Bill Wendling
cf901346da Use "SINT_TO_FP" instead of "UINT_TO_FP" when getting the exponent. This was
causing the limited precision stuff to produce the wrong result for values in
the range [0, 1).

llvm-svn: 62615
2009-01-20 21:17:57 +00:00
Evan Cheng
b3c82db63d Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
llvm-svn: 62600
2009-01-20 19:12:24 +00:00
Bill Wendling
5685c90e04 Shift types need to match.
llvm-svn: 62571
2009-01-20 06:10:42 +00:00
Dan Gohman
ff4c4ab39f Fix a dagcombine to not generate loads of non-round integer types,
as its comment says, even in the case where it will be generating
extending loads. This fixes PR3216.

llvm-svn: 62557
2009-01-20 01:06:45 +00:00
Devang Patel
7c2157602d Verify debug info.
llvm-svn: 62545
2009-01-19 23:21:49 +00:00
Dan Gohman
02b5657666 Remove SDNode's virtual destructor. This makes it impossible for
SDNode subclasses to keep state that requires non-trivial
destructors, however it was already effectively impossible,
since the destructor isn't actually ever called. There currently
aren't any SDNode subclasses affected by this, and in general
it's desireable to keep SDNode objects light-weight.

This eliminates the last virtual member function in the SDNode
class, so it eliminates the need for a vtable pointer, making
SDNode smaller.

llvm-svn: 62539
2009-01-19 22:39:36 +00:00
Dan Gohman
af4e583c93 Fix SelectionDAG::ReplaceAllUsesWith to behave correctly when
uses are added to the From node while it is processing From's
use list, because of automatic local CSE. The fix is to avoid
visiting any new uses.

Fix a few places in the DAGCombiner that assumed that after
a RAUW call, the From node has no users and may be deleted.

This fixes PR3018.

llvm-svn: 62533
2009-01-19 21:44:21 +00:00
Sanjiv Gupta
5a5af71ca2 Few targets like PIC16 wants libcall generation for illegal type i16.
llvm-svn: 62467
2009-01-18 18:25:27 +00:00
Mon P Wang
27ea1af89f Simplify extract element based on comments from Duncan Sands.
llvm-svn: 62459
2009-01-18 06:43:40 +00:00
Mon P Wang
563134282c Simplify extract element of a scalar to vector.
llvm-svn: 62383
2009-01-17 00:07:25 +00:00
Dan Gohman
3d0633627d Instead of adding dependence edges between terminator instructions
and every other instruction in their blocks to keep the terminator
instructions at the end, teach the post-RA scheduler how to operate
on ranges of instructions, and exclude terminators from the range
of instructions that get scheduled.

Also, exclude mid-block labels, such as EH_LABEL instructions, and
schedule code before them separately from code after them. This
fixes problems with the post-RA scheduler moving code past
EH_LABELs.

llvm-svn: 62366
2009-01-16 22:10:20 +00:00
Dan Gohman
4dc9f47c97 Use the getNode() accessor instead of accessing the Node
member directly, which is private as of r55504.

llvm-svn: 62364
2009-01-16 21:47:21 +00:00
Chris Lattner
cfaf556999 new nodes should be added to the worklist, not old nodes.
llvm-svn: 62359
2009-01-16 21:15:56 +00:00
Evan Cheng
c4d19d6e8c CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.
llvm-svn: 62356
2009-01-16 20:57:18 +00:00
Mikhail Glushenkov
49be18cfc6 Registry.h should not depend on CommandLine.h.
Split Support/Registry.h into two files so that we have less to
recompile every time CommandLine.h is changed.

llvm-svn: 62312
2009-01-16 07:02:28 +00:00
Mikhail Glushenkov
5000223556 Delete trailing whitespace.
llvm-svn: 62307
2009-01-16 06:53:46 +00:00
Dan Gohman
c5b1dbdb4e Initial hazard recognizer support in post-pass scheduling. This includes
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.

llvm-svn: 62291
2009-01-16 01:33:36 +00:00
Devang Patel
1ee58c7d8c Validate dbg_* intrinsics before lowering them.
llvm-svn: 62286
2009-01-15 23:41:32 +00:00
Mon P Wang
e235ba591f Added missing support to widen an operand from a bit convert.
llvm-svn: 62285
2009-01-15 22:43:38 +00:00
Dan Gohman
3e0dcbbd15 Generalize the HazardRecognizer interface so that it can be used
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.

llvm-svn: 62284
2009-01-15 22:18:12 +00:00
Rafael Espindola
0aba6c9435 Add the private linkage.
llvm-svn: 62279
2009-01-15 20:18:42 +00:00
Dan Gohman
6fcee67989 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275
2009-01-15 19:20:50 +00:00
Dan Gohman
273ef2ab9f Make getWidenVectorType const; this file was missed in the
previous commit.

llvm-svn: 62266
2009-01-15 17:39:39 +00:00
Dan Gohman
791e6c24db More consts on TargetLowering references.
llvm-svn: 62262
2009-01-15 16:58:17 +00:00
Dan Gohman
9dd6a69768 Use const with TargetLowering references in a few more places.
llvm-svn: 62260
2009-01-15 16:43:02 +00:00
Gabor Greif
feac7ccdbd minor refactoring: use a more specific API
llvm-svn: 62256
2009-01-15 11:10:44 +00:00
Devang Patel
1da8253b35 Removoe MachineModuleInfo methods (and related DebugInfoDesc class hierarchy) that were used to handle debug info.
llvm-svn: 62199
2009-01-13 23:54:55 +00:00
Devang Patel
7a618394f6 Undo previous checkin.
llvm-svn: 62190
2009-01-13 22:54:57 +00:00
Devang Patel
ab5ef6abf1 Use dwarf writer to decide whether the module has debug info or not.
llvm-svn: 62184
2009-01-13 21:25:00 +00:00
Dan Gohman
9e9858781c The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch
this.

It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.

llvm-svn: 62177
2009-01-13 20:24:13 +00:00
Duncan Sands
975f2428ba When replacing uses and the same node is reached
via two paths, process it once not twice, d'oh!
Analysis, testcase and original patch thanks to
Mon Ping Wang.

llvm-svn: 62169
2009-01-13 15:17:14 +00:00
Duncan Sands
439d97a6cb Fix some typos. Also, the WidenedVectors map
was not being cleaned by ExpungeNode.

llvm-svn: 62167
2009-01-13 14:42:39 +00:00
Duncan Sands
8267463dec Correct a comment - this is not a sign extension.
llvm-svn: 62166
2009-01-13 14:04:14 +00:00
Devang Patel
eed0505ed8 Use DebugInfo interface to lower dbg_* intrinsics.
llvm-svn: 62127
2009-01-13 00:35:13 +00:00
Duncan Sands
bcdbfb63dc Rename getABITypeSize to getTypePaddedSize, as
suggested by Chris.

llvm-svn: 62099
2009-01-12 20:38:59 +00:00
Evan Cheng
5e17ea36e1 Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency.
Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet.

llvm-svn: 62074
2009-01-12 03:19:55 +00:00
Evan Cheng
e280fcfbbc CheckForPhysRegDependency should not return copy cost. It's not used. No functionality change.
llvm-svn: 62036
2009-01-11 08:53:35 +00:00
Evan Cheng
411c48b7d2 Duplicated node may produce a non-physical register def.
llvm-svn: 62015
2009-01-09 22:44:02 +00:00
Evan Cheng
7a918ea197 Minor debug output tweak.
llvm-svn: 62005
2009-01-09 20:42:34 +00:00
Devang Patel
7fd7643d23 Request DwarfWriter. This will be used to handle dbg_* intrinsics.
llvm-svn: 61999
2009-01-09 19:11:50 +00:00
Misha Brukman
71c7e40966 Removed trailing whitespace from Makefiles.
llvm-svn: 61991
2009-01-09 16:44:42 +00:00