RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity
77,996 Commits 4 Branches 5 Tags 704 MiB
d842079270
Commit Graph

77996 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Craig Topper
d842079270 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636. 
llvm-svn: 144777
 2011-11-16 05:02:04 +00:00
Evan Cheng
ab9e2ad9c4 Revert r144568 now that r144730 has fixed the fast-isel kill marker bug. 
llvm-svn: 144776
 2011-11-16 04:55:01 +00:00
Nick Lewycky
29efc8f15d Fix typo in test. 
llvm-svn: 144774
 2011-11-16 03:56:38 +00:00
Nick Lewycky
ff690249a9 Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when 
looking at the size of the pointee. Fixes PR11390!

llvm-svn: 144773
 2011-11-16 03:49:48 +00:00
Evan Cheng
65d5df1165 If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges. 
llvm-svn: 144772
 2011-11-16 03:47:42 +00:00
Evan Cheng
27c17a65d1 RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185 
llvm-svn: 144771
 2011-11-16 03:33:08 +00:00
Evan Cheng
d756c3ec65 Process all uses first before defs to accurately capture register liveness. rdar://10449480 
llvm-svn: 144770
 2011-11-16 03:05:12 +00:00
Eli Friedman
c2a46f1a90 Fix testcase. 
llvm-svn: 144769
 2011-11-16 03:03:52 +00:00
Eli Friedman
1f3d774ba4 CONCAT_VECTORS can have more than two operands. PR11389. 
llvm-svn: 144768
 2011-11-16 02:52:39 +00:00
Eli Friedman
ce0cea66b9 Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer. 
llvm-svn: 144767
 2011-11-16 02:43:15 +00:00
Michael J. Spencer
d410d36be0 Remove extra ,. 
llvm-svn: 144759
 2011-11-16 01:36:50 +00:00
Kostya Serebryany
4105068ea9 AddressSanitizer, first commit (compiler module only) 
llvm-svn: 144758
 2011-11-16 01:35:23 +00:00
Michael J. Spencer
8e33446699 Object/Archive: Give Child a operator < for map. 
llvm-svn: 144757
 2011-11-16 01:25:13 +00:00
Michael J. Spencer
796bb719a3 Support/COFF: Add structs and enums from the standard for image files. 
llvm-svn: 144756
 2011-11-16 01:24:57 +00:00
Michael J. Spencer
70bc3d6855 llvm-objdump: Ignore non-objects in archives. 
llvm-svn: 144755
 2011-11-16 01:24:41 +00:00
Kostya Serebryany
dedd750c82 test commit to verify that commit access works (added blank line) 
llvm-svn: 144748
 2011-11-16 01:14:38 +00:00
Owen Anderson
48a129b50e Rename MVT::untyped to MVT::Untyped to match similar nomenclature. 
llvm-svn: 144747
 2011-11-16 01:02:57 +00:00
Andrew Trick
fe618116fc Fix SCEV overly optimistic back edge taken count for multi-exit loops. 
Fixes PR11375: Different results for 'clang++ huh.cpp'...

llvm-svn: 144746
 2011-11-16 00:52:40 +00:00
Chad Rosier
17577c9394 Add FIXME comment. 
llvm-svn: 144743
 2011-11-16 00:32:20 +00:00
Jakob Stoklund Olesen
5ea426cfa8 Enable -widen-vmovs by default. 
This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

llvm-svn: 144734
 2011-11-15 23:53:18 +00:00
Eric Christopher
c9b63af4bb Stabilize the output of the dwarf accelerator tables. Fixes a comparison 
failure during bootstrap with it turned on.

llvm-svn: 144731
 2011-11-15 23:37:17 +00:00
Chad Rosier
71f1bbe1e7 GEPs with all zero indices are trivially coalesced by fast-isel. For example, 
%arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0
%arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134

Prior to this commit, the GEP instruction that defines %arrayidx136 thought that 
%arrayidx135 was a trivial kill.  The GEP that defines %arrayidx135 doesn't 
generate any code and thus %M0 gets folded into the second GEP.  Thus, we need
to look through GEPs with all zero indices.
rdar://10443319

llvm-svn: 144730
 2011-11-15 23:34:05 +00:00
Jim Grosbach
044acb8bee ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727
 2011-11-15 23:19:15 +00:00
Devang Patel
2ef9b806bc Merge ObjCPropertyDebugInfo.html into SourceLevelDebugging.html 
llvm-svn: 144724
 2011-11-15 22:59:54 +00:00
Jim Grosbach
778bed02bb ARM assembly parsing for data type suffices on NEON VMOV aliases. 
llvm-svn: 144722
 2011-11-15 22:54:42 +00:00
Nadav Rotem
d8497a8354 Fix MSVC warnings by adding a cast. 
llvm-svn: 144721
 2011-11-15 22:54:21 +00:00
Nadav Rotem
63be4a26a9 AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code. 
llvm-svn: 144720
 2011-11-15 22:50:37 +00:00
Chris Lattner
026180c6e5 jakob fixed X87 inline asm! 
llvm-svn: 144719
 2011-11-15 22:48:24 +00:00
Chris Lattner
35b9395faf add ImmutableSet/Map dox, patch by Caitlin Sadowski! 
llvm-svn: 144716
 2011-11-15 22:40:14 +00:00
NAKAMURA Takumi
f99c0f0fcd test/CodeGen/X86/dec-eflags-lower.ll: Relax expression for win32 x64. 
llvm-svn: 144714
 2011-11-15 22:30:37 +00:00
Jim Grosbach
b8ebc386df ARM assembly parsing two operand forms for shift instructions. 
llvm-svn: 144713
 2011-11-15 22:27:54 +00:00
Chris Lattner
d6214281c5 add PTX backend info 
llvm-svn: 144711
 2011-11-15 22:23:46 +00:00
Jim Grosbach
d573473cb8 ARM VFP assembly parsing for VADD and VSUB two-operand forms. 
llvm-svn: 144710
 2011-11-15 22:15:10 +00:00
Jim Grosbach
e991d79b50 ARM accept an immediate offset in memory operands w/o the '#'. 
llvm-svn: 144709
 2011-11-15 22:14:41 +00:00
Chris Lattner
a7ceec1f82 some notes. 
llvm-svn: 144708
 2011-11-15 22:13:27 +00:00
Pete Cooper
8441c08e0b Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used 
by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>

llvm-svn: 144705
 2011-11-15 21:57:53 +00:00
Jim Grosbach
8f360855cf ARM enclosing curly braces optional on one-register VLD/VST instruction lists. 
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

llvm-svn: 144701
 2011-11-15 21:45:55 +00:00
Akira Hatanaka
4ca3e2bdad Update section "MIPS Target Improvements" in the llvm 3.0 release notes. 
llvm-svn: 144699
 2011-11-15 21:33:05 +00:00
Jim Grosbach
3c205132ff ARM size suffix on VFP single-precision 'vmov' is optional. 
rdar://10435114

llvm-svn: 144698
 2011-11-15 21:18:35 +00:00
Devang Patel
11c550b1e5 Insert modified DBG_VALUE into LiveDbgValueMap. 
llvm-svn: 144696
 2011-11-15 21:03:58 +00:00
Jim Grosbach
f68b81adb7 Fix typo. 
llvm-svn: 144695
 2011-11-15 21:01:30 +00:00
Jim Grosbach
4d0ad5a4e0 ARM alternate size suffices for VTRN instructions. 
rdar://10435076

llvm-svn: 144694
 2011-11-15 20:49:46 +00:00
Owen Anderson
f71db061ba Fix a misplaced paren bug. 
llvm-svn: 144692
 2011-11-15 20:30:41 +00:00
Jim Grosbach
8987b277cb ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

llvm-svn: 144691
 2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

llvm-svn: 144689
 2011-11-15 20:14:51 +00:00
Jim Grosbach
8b1d4c989c ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

llvm-svn: 144688
 2011-11-15 20:02:06 +00:00
Jim Grosbach
e4933acaa7 Testcase for r144684. 
llvm-svn: 144685
 2011-11-15 19:56:17 +00:00
Jim Grosbach
6dbfffcbf7 Thumb2 two-operand 'mul' instruction wide encoding parsing. 
rdar://10449724

llvm-svn: 144684
 2011-11-15 19:55:16 +00:00
Owen Anderson
35f049f1fb Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
llvm-svn: 144683
 2011-11-15 19:55:00 +00:00
Jim Grosbach
df951fa128 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679
 2011-11-15 19:29:45 +00:00