3 Commits

Author	SHA1	Message	Date
Matt Arsenault	1c34836bdc	AMDGPU: Split x8 and x16 vector loads instead of scalarize ... The one regression in the builtin tests is in the read2 test which now (again) has many extra copies, but this should be solved once the pass is replaced with a DAG combine. llvm-svn: 253974	2015-11-24 12:05:03 +00:00
Matt Arsenault	1adcdc6e96	AMDGPU: Add sdst operand to VOP2b instructions ... The VOP3 encoding of these allows any SGPR pair for the i1 output, but this was forced before to always use vcc. This doesn't yet try to use this, but does add the operand to the definitions so the main change is adding vcc to the output of the VOP2 encoding. llvm-svn: 246358	2015-08-29 07:16:50 +00:00
Tom Stellard	3f1708598e	R600 -> AMDGPU rename ... llvm-svn: 239657	2015-06-13 03:28:10 +00:00