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Commit Graph

24325 Commits

Author SHA1 Message Date
Adrian Prantl
d9d9500a15 IR: Add a setDWOId() method to DICompileUnit.
Tested via clang.

llvm-svn: 248342
2015-09-22 23:21:06 +00:00
Adrian Prantl
83423bf4f7 IR: Fix the return value of DICompileUnit::getDWOId.
llvm-svn: 248341
2015-09-22 23:21:03 +00:00
Aaron Ballman
a8b98ade3c Instead of defining the operator delete() function, it is better to delete the function so that any uses (even from within Node or its subclasses) do not accidentally call it. NFC intended.
llvm-svn: 248320
2015-09-22 21:00:35 +00:00
Ahmed Bougacha
5f15f97d4c [AArch64] Emit clrex in the expanded cmpxchg fail block.
In the comparison failure block of a cmpxchg expansion, the initial
ldrex/ldxr will not be followed by a matching strex/stxr.
On ARM/AArch64, this unnecessarily ties up the execution monitor,
which might have a negative performance impact on some uarchs.

Instead, release the monitor in the failure block.
The clrex instruction was designed for this: use it.

Also see ARMARM v8-A B2.10.2:
"Exclusive access instructions and Shareable memory locations".

Differential Revision: http://reviews.llvm.org/D13033

llvm-svn: 248291
2015-09-22 17:21:44 +00:00
NAKAMURA Takumi
162c68483b Prune trailing whitespaces.
llvm-svn: 248265
2015-09-22 11:19:03 +00:00
NAKAMURA Takumi
28276df470 Reformat blank lines.
llvm-svn: 248263
2015-09-22 11:14:39 +00:00
NAKAMURA Takumi
a6e5b048c7 Reformat comment lines.
llvm-svn: 248262
2015-09-22 11:14:12 +00:00
NAKAMURA Takumi
8c11e8767b Reformat.
llvm-svn: 248261
2015-09-22 11:13:55 +00:00
Matthias Braun
9d8791c829 LiveIntervalAnalysis: Factor common code into splitSeparateComponents; NFC
llvm-svn: 248241
2015-09-22 03:44:41 +00:00
Matthias Braun
d8c97c7d9d Remove declarations for methods that do not exist.
llvm-svn: 248238
2015-09-22 01:52:44 +00:00
NAKAMURA Takumi
8f3d54e1ac Fix r248164. [-Wdocumentation]
llvm-svn: 248237
2015-09-22 01:44:21 +00:00
Stephen Canon
8d99b66558 Remove roundingMode argument in APFloat::mod
Because mod is always exact, this function should have never taken a rounding mode argument.  The actual implementation still has issues, which I'll look at resolving in a subsequent patch.

llvm-svn: 248195
2015-09-21 19:29:25 +00:00
Chandler Carruth
64d752522d [ADT] Remove a couple of the always inline attributes I added.
Based on conversations with Justin and a few others, these constructors
are really useful to have in the executable so that you can call them
from the debugger. After some measurements, these *particular* calls
aren't so problematic as to make them a good tradeoff for always inline.

Please let me know if there are other functions really needed for
debugging. The always inline attribute is a hack that we should only
really employ when it doesn't hurt.

llvm-svn: 248188
2015-09-21 18:02:24 +00:00
Marcello Maggioni
d849f468b0 [DivergenceAnalysis] Separated definition of class into header.
The definition of the DivergenceAnalysis pass was in a CPP
file and wasn't accessible to users of the analysis to get it
through "getAnalysis<>()".
This patch extracts the definition into a separate header that
can be used by users of the analysis to fetch the results.

Patch by Volkan Keles (vkeles@apple.com)

llvm-svn: 248186
2015-09-21 17:58:14 +00:00
James Molloy
30ca0bc2fd Revert "[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def"
This was committed without the code review (http://reviews.llvm.org/D12937) being approved.

This reverts commit r248152.

llvm-svn: 248174
2015-09-21 16:35:08 +00:00
Matt Arsenault
ff8d6555b0 Fix missing C++ mode comment
llvm-svn: 248167
2015-09-21 15:59:41 +00:00
Chad Rosier
432f88b93e [Machine Combiner] Refactor machine reassociation code to be target-independent.
No functional change intended.
Patch by Haicheng Wu <haicheng@codeaurora.org>!

http://reviews.llvm.org/D12887
PR24522

llvm-svn: 248164
2015-09-21 15:09:11 +00:00
Artyom Skrobov
cfadb3d603 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a
hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with
a FIXME: attached.

This patch changes the handling of +t2dsp to be in line with other
architecture extensions.

Following review comments, also updating the description of FeatureDSPThumb2
in ARM.td.

Differential Revision: http://reviews.llvm.org/D12937

llvm-svn: 248152
2015-09-21 12:43:10 +00:00
Craig Topper
e3fc758778 Use makeArrayRef or None to avoid unnecessarily mentioning the ArrayRef type extra times. NFC
llvm-svn: 248140
2015-09-21 05:32:41 +00:00
Craig Topper
fd37494dd2 Don't pass StringRefs around by const reference. Pass by value instead per coding standards. NFC
llvm-svn: 248136
2015-09-21 00:18:00 +00:00
Craig Topper
280987c301 Cleanup places that passed SMLoc by const reference to pass it by value instead. NFC
llvm-svn: 248135
2015-09-20 23:35:59 +00:00
Igor Breger
a833017e0d AVX512: Implemented encoding and intrinsics for vcmpss/sd.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12593

llvm-svn: 248121
2015-09-20 15:15:10 +00:00
Asaf Badouh
4ce11a0a36 [X86][AVX512] extend support in Scalar conversion
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics

Differential Revision: http://reviews.llvm.org/D12665

llvm-svn: 248117
2015-09-20 14:31:19 +00:00
Igor Breger
6c78cd17ac AVX512: vsqrtss/sd encoding and intrinsics implementation.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12102

llvm-svn: 248116
2015-09-20 09:13:41 +00:00
Asaf Badouh
981ab82bef [X86][AVX512DQ] Add fpclass instruction
Differential Revision: http://reviews.llvm.org/D12931

llvm-svn: 248115
2015-09-20 08:46:07 +00:00
Igor Breger
5be1c75e87 AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, vshufi32x4
Added tests for intrinsics.

Differential Revision: http://reviews.llvm.org/D12525

llvm-svn: 248113
2015-09-20 07:18:53 +00:00
Igor Breger
43e0d98a01 AVX512: Implement instructions encoding, lowering and intrinsics
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.

Differential Revision: http://reviews.llvm.org/D11893

llvm-svn: 248111
2015-09-20 06:52:42 +00:00
Rafael Espindola
e32f04d220 This code never uses r_addend, so it can just use Elf_Rel.
llvm-svn: 248040
2015-09-18 21:12:38 +00:00
Davide Italiano
3069215616 [Object/ELF] Change comment to reflect reality.
llvm-svn: 248032
2015-09-18 20:41:15 +00:00
Teresa Johnson
b5092973af Remove couple of new Bitcode enum vals that snuck in via r247927 (NFC)
These are meant to be part of the follow on patch I am sending for
review shortly.

llvm-svn: 248023
2015-09-18 19:38:53 +00:00
Larisse Voufo
d25582bd2b Clean up: Refactoring the hardcoded value of 6 for FindAvailableLoadedValue()'s parameter MaxInstsToScan. (Complete version of r247497. See D12886)
llvm-svn: 248022
2015-09-18 19:14:35 +00:00
James Y Knight
6a6ee2cd7f Make MachineScheduler debug output less confusing.
At least...a little bit.

llvm-svn: 248020
2015-09-18 18:52:20 +00:00
Matthias Braun
8bd54b9028 SelectionDAG: Introduce PersistentID to SDNode for assert builds.
This gives us more human readable numbers to identify nodes in debug
dumps.

Before:
  0x7fcbd9700160: ch = EntryToken

  0x7fcbd985c7c8: i64 = Register %RAX

   ...

      0x7fcbd9700160: <multiple use>
    0x7fcbd985c578: i64,ch = MOV64rm 0x7fcbd985c6a0, 0x7fcbd985cc68, 0x7fcbd985c200, 0x7fcbd985cd90, 0x7fcbd985ceb8, 0x7fcbd9700160<Mem:LD8[@foo]> [ORD=2]

  0x7fcbd985c8f0: ch,glue = CopyToReg 0x7fcbd9700160, 0x7fcbd985c7c8, 0x7fcbd985c578 [ORD=3]

    0x7fcbd985c7c8: <multiple use>
    0x7fcbd985c8f0: <multiple use>
    0x7fcbd985c8f0: <multiple use>
  0x7fcbd985ca18: ch = RETQ 0x7fcbd985c7c8, 0x7fcbd985c8f0, 0x7fcbd985c8f0:1 [ORD=3]

Now:
  t0: ch = EntryToken

  t5: i64 = Register %RAX

    ...

      t0: <multiple use>
    t3: i64,ch = MOV64rm t10, t12, t11, t13, t14, t0<Mem:LD8[@foo]> [ORD=2]

  t6: ch,glue = CopyToReg t0, t5, t3 [ORD=3]

    t5: <multiple use>
    t6: <multiple use>
    t6: <multiple use>
  t7: ch = RETQ t5, t6, t6:1 [ORD=3]

Differential Revision: http://reviews.llvm.org/D12564

llvm-svn: 248010
2015-09-18 17:41:00 +00:00
Yaron Keren
ec99ed2cc1 Simplify SmallBitVector::applyMask by consolidating common code for 32- and 64-bit builds
and assert when mask is too large to apply in the small case,
previously the extra words were silently ignored.
clang-format the entire function to match current code standards.

This is a rewrite of r247972 which was reverted in r247983 due to
warning and possible UB on 32-bits hosts.

llvm-svn: 247993
2015-09-18 15:08:24 +00:00
Aaron Ballman
def3e26caa Reverting r247972 (and subordinate commit r247972) as the 32-bit left-shift is undefined behavior on implementations where uinptr_t is 32-bits. One such platform is Windows, MSVC, x86.
llvm-svn: 247983
2015-09-18 12:18:41 +00:00
David Majnemer
0f63c81aa5 [WinEH] Moved funclet pads should be in relative order
We shifted the MachineBasicBlocks to the end of the MachineFunction in
DFS order.  This will not ensure that MachineBasicBlocks which fell
through to one another will remain contiguous.  Instead, implement
a stable sort algorithm for iplist.

This partially reverts commit r214150.

llvm-svn: 247978
2015-09-18 08:18:07 +00:00
Yaron Keren
c155166785 Simplify SmallBitVector::applyMask by consolidating common code for 32-bit and 64-bit builds.
Extend mask value to 64 bits before taking its complement and assert when mask is
too large to apply in the small case (previously the extra words were silently ignored).

http://reviews.llvm.org/D11890

Patch by James Touton!

llvm-svn: 247972
2015-09-18 06:35:12 +00:00
David Blaikie
adec03e01e [opaque pointer types] Add an explicit pointee type to alias records in the IR
Since aliases actually use and verify their explicit type already, no
further invalid testing is required here. The
invalid.test:ALIAS-TYPE-MISMATCH case catches errors due to emitting a
non-pointee type in the new format or a non-pointer type in the old
format.

llvm-svn: 247952
2015-09-17 22:18:59 +00:00
Matthias Braun
0bcec09bcb Revert "(HEAD -> master, origin/master, origin/HEAD) RegisterPressure: Move LiveInRegs/LiveOutRegs from RegisterPressure to PressureTracker"
This reverts commit r247943.

Accidental commit, code review was not finished yet.

llvm-svn: 247945
2015-09-17 21:12:24 +00:00
Matthias Braun
dfb016bb79 RegisterPressure: Move LiveInRegs/LiveOutRegs from RegisterPressure to PressureTracker
Differential Revision: http://reviews.llvm.org/D12814

llvm-svn: 247943
2015-09-17 21:10:06 +00:00
David Majnemer
de737e6069 [WinEH] Add a funclet layout pass
Windows EH funclets need to be contiguous.  The FuncletLayout pass will
ensure that the funclets are together and begin with a funclet entry MBB.

Differential Revision: http://reviews.llvm.org/D12943

llvm-svn: 247937
2015-09-17 20:45:18 +00:00
Reid Kleckner
5370cf8a53 [WinEH] Make funclet return instrs pseudo instrs
This makes catchret look more like a branch, and less like a weird use
of BlockAddress. It also lets us get away from
llvm.x86.seh.restoreframe, which relies on the old parentfpoffset label
arithmetic.

llvm-svn: 247936
2015-09-17 20:43:47 +00:00
Piotr Padlewski
4a51a0af8a Added MD_invariant_group to LLVMContext
http://reviews.llvm.org/D12926

llvm-svn: 247931
2015-09-17 20:25:07 +00:00
Teresa Johnson
cae4b3b956 Restore "Function bitcode index in Value Symbol Table and lazy reading support"
This reverts commit r247898 (which reverted r247894).

Patch fixed to address two issues exposed by buildbots:
- unused variable warning in NDEBUG mode
- std::initializer_list lifetime issue causing test failures

Original Summary:
Support for including the function bitcode indices in the Value Symbol
Table. This requires writing the VST after the function blocks, which in
turn requires a new VST forward declaration record encoding the offset of
the full VST (which is backpatched to contain the offset after the VST
is written).

This patch also enables the lazy function reader to use the new function
indices out of the VST. This support will be used by ThinLTO as well, which
will be in a follow on patch. Backwards compatibility with older bitcode
files is maintained.

A new test is also included.

The bitcode format (used for the lazy reader as well as the upcoming
ThinLTO patches) came out of discussions with Duncan and others and is
described here:
https://drive.google.com/file/d/0B036uwnWM6RWdnBLakxmeDdOeXc/view

Reviewers: dexonsmith, davidxl, joker.eph

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12536

llvm-svn: 247927
2015-09-17 20:12:00 +00:00
Sanjoy Das
a2013dbe4c [SCEV] Don't repeat method/field names in comment in header; NFC.
llvm-svn: 247918
2015-09-17 19:04:03 +00:00
Reid Kleckner
5eeecd46f0 [WinEH] Add and use hasEHPadSuccessor instead of getLandingPadSuccessor
getLandingPadSuccessor assumes that each invoke can have at most one EH
pad successor, but WinEH invokes can have more than one. Two out of
three callers of getLandingPadSuccessor don't use the returned
landingpad, so we can make them use this simple predicate instead.

Eventually we'll have to circle back and fix SplitKit.cpp so that
register allocation works. Baby steps.

llvm-svn: 247904
2015-09-17 17:19:40 +00:00
Teresa Johnson
f6b3ebd622 Revert "Function bitcode index in Value Symbol Table and lazy reading support"
Temporarily revert to fix some buildbot issues. One is a minor issue
with a variable unused in NDEBUG mode. More concerning are some test
failures on win7 that I need to dig into.

This reverts commit 4e66a74543459832cfd571db42b4543580ae1d1d.

llvm-svn: 247898
2015-09-17 16:19:10 +00:00
Teresa Johnson
41ac0c3883 Function bitcode index in Value Symbol Table and lazy reading support
Summary:
Support for including the function bitcode indices in the Value Symbol
Table. This requires writing the VST after the function blocks, which in
turn requires a new VST forward declaration record encoding the offset of
the full VST (which is backpatched to contain the offset after the VST
is written).

This patch also enables the lazy function reader to use the new function
indices out of the VST. This support will be used by ThinLTO as well, which
will be in a follow on patch. Backwards compatibility with older bitcode
files is maintained.

A new test is also included.

The bitcode format (used for the lazy reader as well as the upcoming
ThinLTO patches) came out of discussions with Duncan and others and is
described here:
https://drive.google.com/file/d/0B036uwnWM6RWdnBLakxmeDdOeXc/view

Reviewers: dexonsmith, davidxl, joker.eph

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12536

llvm-svn: 247894
2015-09-17 15:52:30 +00:00
Diego Novillo
3ccc9d9f6a GCC AutoFDO profile reader - Initial support.
This adds enough machinery to support reading simple GCC AutoFDO
profiles. It now supports reading flat profiles (no function calls).
Subsequent patches will add support for:

- Inlined calls (in particular, the inline call stack is not traversed
  to accumulate samples).

- Working sets and modules. These are used mostly for GCC's LIPO
  optimizations, so they're not needed in LLVM atm. I'm not sure that
  we will ever need them. For now, I've if0'd around the calls.

The patch also adds support in GCOV.h for gcov version V704 (generated
by GCC's profile conversion tool).

llvm-svn: 247874
2015-09-17 00:17:24 +00:00
Eric Christopher
a096f8ec12 constify the Function parameter to the TTI creation callback and
propagate to all callers/users/etc.

llvm-svn: 247864
2015-09-16 23:38:13 +00:00