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2229 Commits

Author SHA1 Message Date
Bill Wendling
16e7d7bf2f Add support for using the `!if' operator when initializing variables: 
class A<bit a, bits<3> x, bits<3> y> {
    bits<3> z;
    let z = !if(a, x, y);
  }

The variable z will get the value of x when 'a' is 1 and 'y' when a is '0'.

llvm-svn: 121666
 2010-12-13 01:46:19 +00:00
Bill Wendling
ea9c4c1e11 Move <map> include out of .h and into .cpp. 
llvm-svn: 121661
 2010-12-13 01:05:54 +00:00
Bill Wendling
1b8163a33e Merge DEBUG statements. 
llvm-svn: 121660
 2010-12-13 01:03:49 +00:00
Chris Lattner
8e4bbafeb3 eliminate the Records global variable, patch by Garrison Venn! 
llvm-svn: 121659
 2010-12-13 00:23:57 +00:00
Chris Lattner
5e7e7c817c clean up RecordKeeper::getAllDerivedDefinitions, patch by Garrison Venn! 
llvm-svn: 121658
 2010-12-13 00:20:52 +00:00
Bill Wendling
59f4c83400 Get rid of ellipses. 
llvm-svn: 121589
 2010-12-10 22:54:30 +00:00
Jim Grosbach
a378c43eae Thumb unconditional branch binary encoding. rdar://8754994 
llvm-svn: 121496
 2010-12-10 18:21:33 +00:00
Jim Grosbach
905301a7d8 Thumb conditional branch binary encodings. rdar://8745367 
llvm-svn: 121493
 2010-12-10 17:13:40 +00:00
Bob Wilson
f99cd09e3f The Neon vqdmlsl_lane and vqdmlal_lane intrinsics have 4 arguments, not 3. 
llvm-svn: 121469
 2010-12-10 06:37:53 +00:00
Jim Grosbach
57d420438a Thumb needs a few different encoding schemes for branch targets. Rename 
t_brtarget to be more specific.

llvm-svn: 121398
 2010-12-09 19:01:46 +00:00
Bob Wilson
3c35e2ab2f 80-column fixes. 
llvm-svn: 121395
 2010-12-09 18:43:35 +00:00
Bob Wilson
bd5b0c9ec6 Add a license comment to the generated arm_neon.h header. 
Remove the previous header.  I don't think we need to expose to end users
that we use TableGen to produce our version of arm_neon.h, and that header
was also using doubleslash comments which could be a problem when using it
in strict C89 compilations.

llvm-svn: 121390
 2010-12-09 18:31:01 +00:00
Michael J. Spencer
15483143ec Support/MemoryBuffer: Replace all uses of std::string *ErrMsg with error_code &ec. And fix clients. 
llvm-svn: 121379
 2010-12-09 17:36:48 +00:00
Bill Wendling
cd8fdfd65f The BLX instruction is encoded differently than the BL, because why not? In 
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.

Attempt to get the encoding at slightly more correct with this.

llvm-svn: 121336
 2010-12-09 00:39:08 +00:00
Bill Wendling
9756f7c7b0 Support the "target" encodings for the CB[N]Z instructions. 
llvm-svn: 121308
 2010-12-08 23:01:43 +00:00
Bob Wilson
8c693a934a Add operators for "_lane" variants of some saturating Neon multiply intrinsics 
so they can be implemented without separate clang builtins.

llvm-svn: 121299
 2010-12-08 22:36:08 +00:00
Bob Wilson
b258f6e80b Add operators for vabdl and vabal so they can be implemented without builtins. 
llvm-svn: 121287
 2010-12-08 21:39:04 +00:00
Bob Wilson
368438b3ac Remove unused function parameter. 
llvm-svn: 121286
 2010-12-08 21:39:00 +00:00
Bob Wilson
9cb69260e2 Add an operator for vaba so it can be implemented using vabd. 
llvm-svn: 121276
 2010-12-08 20:09:10 +00:00
Bill Wendling
24e6d5a4f2 Use this new fangled StringSwitch technology. 
llvm-svn: 121273
 2010-12-08 20:02:49 +00:00
Bill Wendling
3e1be94d7e Cleanup table a bit. 
llvm-svn: 121250
 2010-12-08 13:03:15 +00:00
Bill Wendling
dac1f24d98 Add support for loading from a constant pool. 
llvm-svn: 121226
 2010-12-08 01:57:09 +00:00
Bob Wilson
dd1d9cf3b6 Add operators for vadd[lw] and vsub[lw] 
so they can be implemented without clang builtins.

llvm-svn: 121213
 2010-12-08 00:14:04 +00:00
Bob Wilson
937fe73ee2 Add operators for vmlal{_n,_lane} and vmlsl{_n,_lane} 
so they can be implemented without clang builtins.

llvm-svn: 121209
 2010-12-07 23:53:37 +00:00
Bob Wilson
8182bc40cd Emit vmovl intrinsics first in the arm_neon.h header 
so they can be used in the implementations of other intrinsics.

llvm-svn: 121208
 2010-12-07 23:53:32 +00:00
Jim Grosbach
f3557afc0f Add source Record* reference to PatternToMatch. Allows better diagnostics. 
llvm-svn: 121196
 2010-12-07 23:05:49 +00:00
Bob Wilson
93b8add7dd Add an operator for vdup_lane so it can be implemented without a clang builtin. 
llvm-svn: 121190
 2010-12-07 22:39:24 +00:00
Bob Wilson
9d8115889c Add an operator for vmull_lane so it can be implemented without a clang builtin. 
llvm-svn: 121187
 2010-12-07 22:02:48 +00:00
Jim Grosbach
ffd52cc18a Remove reference to the CMPz instruction patterns for ARM. 
llvm-svn: 121180
 2010-12-07 20:44:33 +00:00
Bob Wilson
8079f3377d Add new built-in operations for vmull and vmull_n 
so they can be implemented without requiring clang builtins.
Radar 8446238.

llvm-svn: 121173
 2010-12-07 20:02:45 +00:00
Jim Grosbach
6795da6388 Trailing whitespace. 
llvm-svn: 121167
 2010-12-07 19:36:07 +00:00
Jim Grosbach
142274a320 Change assert to diagnostic. Message still needs work, but it's better than 
an assert, at least.

llvm-svn: 121166
 2010-12-07 19:35:36 +00:00
Bob Wilson
f909f96f2b Add an OpReinterpret operation to TableGen's NeonEmitter. 
An OpReinterpret entry is handled by translating it to OpCast intrinsics for
all combinations of source and destination types with the same total size.
This will be used to generate all the vreinterpret intrinsics.

llvm-svn: 121087
 2010-12-07 01:12:23 +00:00
Bob Wilson
6492963708 Fix whitespace. 
llvm-svn: 121086
 2010-12-07 01:12:19 +00:00
Jim Grosbach
2d361b9318 Add fixup for Thumb1 BL/BLX instructions. 
llvm-svn: 121072
 2010-12-06 23:57:07 +00:00
Bob Wilson
5917f1a762 Remove trailing whitespace. 
llvm-svn: 120891
 2010-12-04 04:40:15 +00:00
Bob Wilson
8015024bdf Get Neon intrinsic names from the new "Name" field in the tblgen records 
instead of just converting the record name to lowercase.

llvm-svn: 120809
 2010-12-03 17:19:39 +00:00
Bill Wendling
01e67a2a03 I did it wrong. Don't disregard these encodings here. 
llvm-svn: 120786
 2010-12-03 02:25:59 +00:00
Bill Wendling
fad63b8ad2 Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gpr 
instructions. They are handled as special moves, but encoded as a normal move.

llvm-svn: 120779
 2010-12-03 01:55:30 +00:00
Bob Wilson
2e2ccbe986 Add support for "_lane" variants of VMUL, VMLA, and VMLS Neon intrinsics. 
llvm-svn: 120764
 2010-12-03 00:34:12 +00:00
Bob Wilson
73a62b36c6 Support using macros for Neon intrinsics implemented without builtins. 
Intrinsics implemented with Clang builtins could already be implemented as
either inline functions or macros, but intrinsics implemented directly
(without builtins) could only be inline functions.

llvm-svn: 120763
 2010-12-03 00:34:09 +00:00
Bob Wilson
a6ebc72f34 Simplify code in Neon intrinsics. No functional changes intended. 
For most intrinsics, there is no need to allocate a temporary to hold the
result value; just return it directly.

llvm-svn: 120695
 2010-12-02 07:44:23 +00:00
Bob Wilson
1410cd5668 Assign arguments of Neon intrinsic macros to local temporaries. 
Since we're casting them for the calls to the builtins, we need this to
make sure their types get checked in the same way they would if the intrinsics
were implemented as inline functions.

llvm-svn: 120693
 2010-12-02 07:10:39 +00:00
Bob Wilson
1beac04144 Use statement expressions in Neon intrinsics defined as macros. 
This is in preparation for adding assignments to temporaries to ensure
that the proper type checking is done.

llvm-svn: 120649
 2010-12-02 02:42:51 +00:00
Bob Wilson
59b1977d0a Add casts for splatted scalars in calls to Neon builtins. 
llvm-svn: 120641
 2010-12-02 01:18:23 +00:00
Bob Wilson
7680d2f36a Add a missing cast for Neon vsbl results. 
The bitwise operations are always done with unsigned values, but the result may
be signed.

llvm-svn: 120640
 2010-12-02 01:18:20 +00:00
Bob Wilson
c7d49b591c Add another missing cast for Neon vcombine results. 
llvm-svn: 120639
 2010-12-02 01:18:18 +00:00
Bob Wilson
f01547ed73 Add casts in arm_neon.h for result values in inline functions as well as macros. 
We should not rely on lax-vector-conversions for these intrinsics to work.

llvm-svn: 120638
 2010-12-02 01:18:15 +00:00
Bob Wilson
d28c6da501 Avoid "char" for Neon vector elements; make it explicitly signed (or unsigned). 
llvm-svn: 120632
 2010-12-02 00:24:59 +00:00
Bob Wilson
b475c5a1ff Cast scalar results of Neon macros to the correct type. 
llvm-svn: 120631
 2010-12-02 00:24:56 +00:00
Bob Wilson
b3f9b6c2d5 Add explicit casts for vector arguments to Neon builtins. 
This avoids warnings with -Wvector-conversions.  Radar 8228022.

llvm-svn: 120597
 2010-12-01 19:49:58 +00:00
Bob Wilson
b2affb91cd Add some comments for TableGen's NeonEmitter. 
llvm-svn: 120596
 2010-12-01 19:49:56 +00:00
Bob Wilson
84b6b4c00e Cleanup: simplify checks for integers between 2 and 4. 
llvm-svn: 120595
 2010-12-01 19:49:51 +00:00
Jim Grosbach
b2a12afa5f Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR 
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594
 2010-12-01 19:47:31 +00:00
Owen Anderson
5aff471eb8 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the 
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481
 2010-11-30 22:45:47 +00:00
Owen Anderson
5f7b3e919b Add encoding support for Thumb2 PLD and PLI instructions. 
llvm-svn: 120449
 2010-11-30 19:19:31 +00:00
Jim Grosbach
7ae5c75ab7 The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e., 
no extra encoding information), so we no longer need to special case them
here.

llvm-svn: 120444
 2010-11-30 19:08:32 +00:00
Jim Grosbach
6a976d0827 Tidy up. 
llvm-svn: 120443
 2010-11-30 19:00:13 +00:00
Jim Grosbach
d79a0ce6e7 Delete a few no longer needed references to pseudos. 
llvm-svn: 120441
 2010-11-30 18:56:13 +00:00
Bob Wilson
f5eece615c Fix the encoding of VLD4-dup alignment. 
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358
 2010-11-30 00:00:42 +00:00
Jim Grosbach
89e90b7310 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00
Jim Grosbach
71042b51a1 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

llvm-svn: 120320
 2010-11-29 21:28:32 +00:00
Michael J. Spencer
4a63404543 I swear I did a make clean and make before committing all this... 
llvm-svn: 120304
 2010-11-29 18:47:54 +00:00
Michael J. Spencer
d5ec932c3a Merge System into Support. 
llvm-svn: 120298
 2010-11-29 18:16:10 +00:00
Bob Wilson
77071bcf8a Fix copy-and-paste error in exception message. 
llvm-svn: 120033
 2010-11-23 19:38:34 +00:00
Jason W Kim
331b7407c8 Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM. 
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.

llvm-svn: 119760
 2010-11-18 23:37:15 +00:00
Bill Wendling
0139d909bd Give the exclamation point a name instead of a number. 
llvm-svn: 119759
 2010-11-18 23:36:54 +00:00
Bob Wilson
a9561a6257 Change the 'x' type modifier for Neon intrinsics to force a signed integer. 
This makes it symmetric with the 'u' modifier that forces an unsigned type.
This is needed for unsigned vector shifts, where the shift amount still needs
to be signed.  PR8482 (Radar 8603521).

llvm-svn: 119742
 2010-11-18 21:43:22 +00:00
Evan Cheng
ce610bd6b3 Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, 
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548
 2010-11-17 20:13:28 +00:00
Bill Wendling
f0a1acba8c Proper encoding for VLDM and VSTM instructions. The register lists for these 
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460
 2010-11-17 04:32:08 +00:00
Bob Wilson
2f7de3aad6 Use new neon_vector_type and neon_polyvector_type attributes for Neon vectors. 
llvm-svn: 119406
 2010-11-16 23:57:06 +00:00
Bob Wilson
b48fd4816a Change Neon polynomial types to be signed to match GCC. 
llvm-svn: 119405
 2010-11-16 23:57:03 +00:00
Bob Wilson
f2bb931c9f Refactor to new GetNumElements function. 
No functional change.

llvm-svn: 119404
 2010-11-16 23:57:01 +00:00
Bob Wilson
efff1285d2 Tidy up some things in <arm_neon.h>. 
Stop defining types with "__neon_" prefixes and then using typedefs without
the prefix; there's no reason to do that anymore.  Remove types that combine
multiple Neon vectors and treat them as a single long vector; they are not
used.

llvm-svn: 119369
 2010-11-16 19:39:14 +00:00
Bob Wilson
808941eb3b Reapply "Stop using struct wrappers for Neon vector types in <arm_neon.h>." 
I've temporarily disabled the failing clang test.

llvm-svn: 119367
 2010-11-16 19:16:06 +00:00
Bob Wilson
e1e6afe51b Revert "Stop using struct wrappers for Neon vector types in <arm_neon.h>." 
It's breaking buildbots.

llvm-svn: 119363
 2010-11-16 18:43:07 +00:00
Bob Wilson
c33bc803b5 Stop using struct wrappers for Neon vector types in <arm_neon.h>. 
Thanks to Nate Begeman for an earlier version of this patch.

llvm-svn: 119358
 2010-11-16 18:17:03 +00:00
Bill Wendling
b450d320ec Encode the multi-load/store instructions with their respective modes ('ia', 
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310
 2010-11-16 01:16:36 +00:00
Chris Lattner
de919e1958 pull the code to get the operand value out of the loop. 
llvm-svn: 119130
 2010-11-15 07:09:28 +00:00
Chris Lattner
af5f044932 split the giant encoder loop into two new helper functions. 
llvm-svn: 119129
 2010-11-15 06:59:17 +00:00
Chris Lattner
0812a5ee5d reduce nesting and minor cleanups, no functionality change. 
llvm-svn: 119128
 2010-11-15 06:42:13 +00:00
Chris Lattner
b2daeac125 add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
 2010-11-15 05:19:05 +00:00
Jim Grosbach
cc8e5dc0c6 ARM fixup encoding for direct call instructions (BL). 
llvm-svn: 118829
 2010-11-11 20:05:40 +00:00
Owen Anderson
f2e9cc82db Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction. 
Not yet used.

llvm-svn: 118759
 2010-11-11 01:19:24 +00:00
Dan Gohman
04e46fa78b Rename AccessesArguments and AccessesArgumentsReadonly, and rewrite 
their comments.

llvm-svn: 118696
 2010-11-10 18:30:00 +00:00
Dan Gohman
357342a9b8 Translate IntrReadArgMem to AccessesArgumentsReadonly. 
llvm-svn: 118622
 2010-11-09 20:07:20 +00:00
Chris Lattner
3ccd1e1530 pass literals like $$1 through to the asm matcher. This isn't right yet, but doesn't hurt. 
llvm-svn: 118359
 2010-11-06 22:06:03 +00:00
Chris Lattner
4834890f0a add (and document) the ability for alias results to have 
fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352
 2010-11-06 19:57:21 +00:00
Chris Lattner
c0e756dc47 generalize alias support to allow the result of an alias to 
add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350
 2010-11-06 19:25:43 +00:00
Chris Lattner
637f4910c3 fix a bug where we had an implicit assumption that the 
result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334
 2010-11-06 08:20:59 +00:00
Chris Lattner
ec0ef3385d fix some bugs in the alias support, unblocking changing of "clr" aliases 
from c++ hacks to proper .td InstAlias definitions.  Change them!

llvm-svn: 118330
 2010-11-06 07:31:43 +00:00
Chris Lattner
5d1361e9ed Reimplement BuildResultOperands to be in terms of the result instruction's 
operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.

llvm-svn: 118329
 2010-11-06 07:14:44 +00:00
Chris Lattner
8980fe2e61 implement more checking to reject things like: 
(someinst GR16:$foo, GR32:$foo)

Reimplement BuildAliasOperandReference to be correctly
based on the names of operands in the result pattern,
instead of on the instruction operand definitions.

llvm-svn: 118328
 2010-11-06 07:06:09 +00:00
Chris Lattner
79e558f9c5 decode and validate instruction alias result definitions. 
llvm-svn: 118327
 2010-11-06 06:54:38 +00:00
Chris Lattner
9365c2366f simplify 
llvm-svn: 118326
 2010-11-06 06:45:08 +00:00
Chris Lattner
b6cc82ecd7 fix another fixme, replacing a string with a semantic pointer. 
llvm-svn: 118325
 2010-11-06 06:43:11 +00:00
Chris Lattner
99f3490b0c disolve a hack, having CodeGenInstAlias decode the alias in the .td 
file instead of the asmmatcher.

llvm-svn: 118324
 2010-11-06 06:39:47 +00:00
Duncan Sands
3bf2a701a5 In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
 2010-11-04 10:49:57 +00:00
Chris Lattner
a55b12911d partition operand processing between aliases and instructions. 
Right now the code is partitioned but the behavior is the same.
This should be improved in the near future.   This removes some
uses of TheOperandList.

llvm-svn: 118232
 2010-11-04 02:11:18 +00:00
Chris Lattner
21179e333e pull name slicing out of BuildInstructionOperandReference so 
it doesn't do any lexical stuff anymore.

llvm-svn: 118230
 2010-11-04 01:58:23 +00:00
Chris Lattner
c30032c0c0 cleanups. 
llvm-svn: 118228
 2010-11-04 01:55:23 +00:00
Chris Lattner
fcdb263fa4 replace SrcOpNum with SrcOpName, eliminating a numering dependency 
on the incoming operand list.  This also makes the code simpler.

llvm-svn: 118225
 2010-11-04 01:42:59 +00:00
Chris Lattner
b0b3157619 strength reduce some code, resolving a fixme. 
llvm-svn: 118219
 2010-11-04 00:57:06 +00:00
Chris Lattner
9ae6cce0fe take a big step to making aliases more general and less of a hack: 
now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.

llvm-svn: 118217
 2010-11-04 00:43:46 +00:00
Jim Grosbach
7426448b7c Support generating an MC'ized CodeEmitter directly. Maintain a reference to the 
Fixups list for the instruction so the operand encoders can add to it as
needed.

llvm-svn: 118206
 2010-11-03 23:38:14 +00:00
Chris Lattner
5280a84fef rename Operand -> AsmOperand for clarity. 
llvm-svn: 118190
 2010-11-03 19:47:34 +00:00
Duncan Sands
f6e5e02c9b Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Jim Grosbach
c10d3f3d4b Break ARM addrmode4 (load/store multiple base address) into its constituent 
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137
 2010-11-03 01:01:43 +00:00
Chris Lattner
d3f7a5d3bd Completely reject instructions that have an operand in their 
ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119
 2010-11-02 23:40:41 +00:00
Chris Lattner
76b970b846 make MatchableInfo::Validate reject instructions (like LDR_PRE in ARM) 
that have complicated tying going on.

llvm-svn: 118112
 2010-11-02 23:18:43 +00:00
Chris Lattner
db83b4f486 rewrite EmitConvertToMCInst to iterate over the MCInst operands, 
filling them in one at a time.  Previously this iterated over the
asmoperands, which left the problem of "holes".  The new approach
simplifies things.

llvm-svn: 118104
 2010-11-02 22:55:03 +00:00
Chris Lattner
bba7ee13c0 merge two large parallel loops in EmitConvertToMCInst, no change 
in the generated .inc files.

llvm-svn: 118083
 2010-11-02 21:49:44 +00:00
Chris Lattner
8759d96b7a a bunch of random cleanup, move a helper to CGT where it belongs. 
llvm-svn: 118031
 2010-11-02 18:10:06 +00:00
Jim Grosbach
d6df785c6d Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke 
assumptions about stack layout. Specifically, LR must be saved next to FP.

llvm-svn: 118026
 2010-11-02 17:35:25 +00:00
Chris Lattner
0ee95ca723 add and update comments. 
llvm-svn: 118025
 2010-11-02 17:34:28 +00:00
Chris Lattner
6f1fec971e refactor/cleanup MatchableInfo by eliminating the Tokens array, 
merging it into a Token field in Operand, and moving the first
token to an explicit mnemonic field.  These were parallel
arrays before (except for the mnemonic) which kept confusing me.

llvm-svn: 118024
 2010-11-02 17:30:52 +00:00
Chris Lattner
13ad624c70 rename operands -> asmoperands to be more descriptive. 
llvm-svn: 117993
 2010-11-02 01:03:43 +00:00
Jim Grosbach
0b563b9b72 Tidy up. 
llvm-svn: 117987
 2010-11-02 00:16:39 +00:00
Chris Lattner
032b91c666 fix computation of ambiguous instructions to not ignore the mnemonic. 
FWIW, X86 has 254 ambiguous instructions.

llvm-svn: 117979
 2010-11-01 23:57:23 +00:00
Chris Lattner
1bdba218ef give MatchableInfo::Operand a constructor 
llvm-svn: 117968
 2010-11-01 23:08:02 +00:00
Chris Lattner
81d051481e Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Chris Lattner
c211fb27e2 rename InstructionInfo -> MatchableInfo since it now 
represents InstAliases as well.  Rename 
isAssemblerInstruction -> Validate since that is what
it does (modulo the ARM $lane hack).

llvm-svn: 117899
 2010-11-01 05:06:45 +00:00
Chris Lattner
8105d0ff81 refactor initialization of InstructionInfo to be sharable between 
instructions and InstAliases.  Start creating InstructionInfo's
for Aliases.

llvm-svn: 117898
 2010-11-01 04:53:48 +00:00
Chris Lattner
0a4807eefc make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner
87c0d54fed refactor InstructionInfo to not have a pointer to CodeGenInstruction 
member, and make isAssemblerInstruction() a method (pushing some code
around inside it).

llvm-svn: 117895
 2010-11-01 04:34:44 +00:00
Chris Lattner
c746d18c42 define a new CodeGenInstAlias. It has an asmstring and operand list for now, 
todo: the result field.

llvm-svn: 117894
 2010-11-01 04:05:41 +00:00
Chris Lattner
45b1a1649c factor the operand list (and related fields/operations) out of 
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
 2010-11-01 04:03:32 +00:00
Chris Lattner
88f746114f avoid needless throw/catch/rethrow, stringref'ize some simple stuff. 
llvm-svn: 117892
 2010-11-01 03:19:09 +00:00
Chris Lattner
d57d9e862d eliminate the old InstFormatName which is always "AsmString", 
simplify CodeGenInstruction. No functionality change.

llvm-svn: 117891
 2010-11-01 02:15:23 +00:00
Chris Lattner
a8d1d91f41 all predicates on an MnemonicAlias must be AssemblerPredicates. 
llvm-svn: 117890
 2010-11-01 02:09:21 +00:00
Chris Lattner
22f9108208 change the singleton register handling code to be based on Record*'s 
instead of strings, simplifying it.

llvm-svn: 117889
 2010-11-01 01:47:07 +00:00
Chris Lattner
359e5c93e8 Give AsmMatcherInfo a CodeGenTarget, which simplifies a bunch of 
argument passing.  Consolidate all SingletonRegister detection
and handling into a new 
InstructionInfo::getSingletonRegisterForToken method instead of
having it scattered about.  No change in generated .inc files.

llvm-svn: 117888
 2010-11-01 01:37:30 +00:00
Chris Lattner
0a33c519da move FlattenVariants out of AsmMatcherEmitter into a shared 
CodeGenInstruction::FlattenAsmStringVariants method.  Use it
to simplify the code in AsmWriterInst, which now no longer 
needs to worry about variants.

llvm-svn: 117886
 2010-11-01 01:07:14 +00:00
Chris Lattner
466a3f6029 add a FIXME, $lane in ARM is an issue that needs to be resolved before 
this can start rejecting instructions.

llvm-svn: 117885
 2010-11-01 00:51:32 +00:00
Chris Lattner
9da275f86b reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Chris Lattner
4e42d39402 fix a crash on: 
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {

we now get:

X86InstrCompiler.td:653:52: error: Expected class, def, defm, multiclass or let definition
let Constraints = "$val = $dst", Defs = [EFLAGS] in, isCodeGenOnly = 1 {
                                                   ^

llvm-svn: 117863
 2010-10-31 19:27:15 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner
5d088218e5 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner
01acd65875 reapply r117858 with apparent editor malfunction fixed (somehow I 
got a dulicated line).

llvm-svn: 117860
 2010-10-31 19:10:56 +00:00
Chris Lattner
8132a182e7 revert r117858 while I check out a failure I missed. 
llvm-svn: 117859
 2010-10-31 19:05:32 +00:00
Chris Lattner
70b05a5b88 the asm matcher can't handle operands with modifiers (like ${foo:bar}). 
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
 2010-10-31 18:48:12 +00:00
Chris Lattner
19ccfc3d63 have GetAliasRequiredFeatures get its features from 
AsmMatcherInfo so we don't have two places that know the
feature -> enum mapping.  No functionality change.

llvm-svn: 117845
 2010-10-30 20:15:02 +00:00
Chris Lattner
17980631fb simplify code that creates SubtargetFeatureInfo, ensuring that features 
that are only used by MnemonicAliases will be found.

llvm-svn: 117844
 2010-10-30 20:07:57 +00:00
Chris Lattner
d4ea8ee6f2 fix a fixme in stringmatcher, having it generate nice looking code if the 
'tomatch' code contains \n's.

llvm-svn: 117843
 2010-10-30 19:57:17 +00:00
Chris Lattner
aace31ce48 fix typos and some serious bugs in feature handling (but not for 
cases that are currently exercised).  Thanks to Frits van Bommel for
the great review!

llvm-svn: 117840
 2010-10-30 19:47:49 +00:00
Chris Lattner
49227ad505 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner
15e92ddd01 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner
cce5ecf2cc fix build problem 
llvm-svn: 117828
 2010-10-30 18:57:07 +00:00
Chris Lattner
aaa72fa2af diagnose targets that define two alises with the same 'from' mnemonic 
with a useful error message instead of having tblgen explode with an 
assert.

llvm-svn: 117827
 2010-10-30 18:56:12 +00:00
Chris Lattner
3daf6d69dc emit the mnemonic aliases in their own helper function instead of 
inline into MatchInstructionImpl.

llvm-svn: 117826
 2010-10-30 18:48:18 +00:00
Chris Lattner
7c61e4bca2 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Jim Grosbach
91b6672682 trailing whitespace 
llvm-svn: 117724
 2010-10-29 22:13:48 +00:00
Chris Lattner
bd838d16e5 fix the asmmatcher generator to handle targets with no RegisterPrefix 
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
 2010-10-28 21:28:42 +00:00
Evan Cheng
44d2802e1d Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Owen Anderson
9437a20a72 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Kevin Enderby
a53cc6a764 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Benjamin Kramer
0113dd35a8 Constify another 2 disassembler tables. 
llvm-svn: 117208
 2010-10-23 09:28:42 +00:00
Benjamin Kramer
ed68a7877c Make the disassembler tables const so they end up in read-only memory. 
llvm-svn: 117206
 2010-10-23 09:10:44 +00:00
Mikhail Glushenkov
858566ac15 Remove -llvmc-temp-hack from tblgen. 
llvm-svn: 117197
 2010-10-23 07:32:53 +00:00
Mikhail Glushenkov
7b1676ee96 Syntax tweak in llvmc: (something [a,b,c]) -> (something a, b, c). 
llvm-svn: 117196
 2010-10-23 07:32:46 +00:00
Mikhail Glushenkov
f04e60720e Trailing whitespace. 
llvm-svn: 117195
 2010-10-23 07:32:37 +00:00
Benjamin Kramer
9e988fe81e Make some symbols static, move classes into anonymous namespaces. 
llvm-svn: 117111
 2010-10-22 17:35:07 +00:00
Anders Carlsson
cb8b02dd95 Add a way to emit StringSwitch of clang attribute spellings. 
llvm-svn: 116899
 2010-10-20 01:21:53 +00:00
Oscar Fuentes
a6ffccab95 Build with RTTI and exceptions disabled. Only in GCC for now. 
llvm-svn: 116682
 2010-10-17 02:26:16 +00:00
Jim Grosbach
67f94c42d8 ARM mode encoding information for UBFX and SBFX instructions. 
llvm-svn: 116588
 2010-10-15 17:15:16 +00:00
Jim Grosbach
1699d40f80 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
 2010-10-13 21:00:04 +00:00
Jim Grosbach
8f0bea85bf Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach
394bc160f9 Allow targets to optionally specify custom binary encoder functions for 
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.

llvm-svn: 116353
 2010-10-12 22:21:57 +00:00
Cameron Esfahani
71cdbd5d44 Fix spelling error. 
llvm-svn: 116282
 2010-10-12 00:21:05 +00:00
Jim Grosbach
06a0fb7aff The assert() should reference to machine instr operand number, too. 
llvm-svn: 116243
 2010-10-11 21:41:31 +00:00
Jim Grosbach
bfc337878b Make sure to use the machine instruction operand number. It doesn't always 
map one-to-one with the CodeGenInstruction operand number.

llvm-svn: 116238
 2010-10-11 21:31:22 +00:00
Jim Grosbach
eded540b87 trailing whitespace cleanup 
llvm-svn: 116215
 2010-10-11 19:38:01 +00:00
Jim Grosbach
8fae045502 When figuring out which operands match which encoding fields in an instruction, 
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).

llvm-svn: 116211
 2010-10-11 18:25:51 +00:00
Jim Grosbach
fb59963159 A few 80 column cleanups 
llvm-svn: 116069
 2010-10-08 18:13:57 +00:00
Jim Grosbach
507bebdd8a trailing whitespace 
llvm-svn: 116068
 2010-10-08 18:09:59 +00:00
Daniel Dunbar
8ac0e27ca6 Fix -Asserts warning. 
llvm-svn: 116030
 2010-10-08 02:07:22 +00:00
Jim Grosbach
df2ff926a6 Make <target>CodeEmitter::getBinaryCodeForInstr() a const method. 
llvm-svn: 116018
 2010-10-08 00:21:28 +00:00
Jim Grosbach
504d7b7d8b Move checking for t2MOVCCi16 to the right place. 
llvm-svn: 115994
 2010-10-07 22:14:01 +00:00
Nick Lewycky
2d8ea609e1 Fix typo in comment. 
llvm-svn: 115986
 2010-10-07 21:55:16 +00:00
Dan Gohman
6645ce3f75 Move tool_output_file into its own file. 
llvm-svn: 115973
 2010-10-07 20:32:40 +00:00
Jim Grosbach
04523be385 trailing whitespace 
llvm-svn: 115923
 2010-10-07 16:56:28 +00:00
Jim Grosbach
c0a61c0796 Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode. 
llvm-svn: 115890
 2010-10-07 00:53:56 +00:00
Jim Grosbach
1e2566c20d Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. 
llvm-svn: 115884
 2010-10-07 00:42:42 +00:00
Jim Grosbach
04a4f7c5d9 Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling. 
llvm-svn: 115841
 2010-10-06 21:17:07 +00:00
Chris Lattner
0bc415a491 Generalize tblgen's dag parsing logic to handle arbitrary expressions 
as the operator of the dag.  Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).

Unfortunately, this runs afoul of an idiom being used by llvmc.  It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo.  With this change, this is parsed as a [1,2,3] 
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.

llvm-svn: 115742
 2010-10-06 04:55:48 +00:00
Chris Lattner
048fc51b83 cleanups 
llvm-svn: 115739
 2010-10-06 04:31:40 +00:00
Chris Lattner
84846b71af remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places 
where !cast is just as short.

llvm-svn: 115722
 2010-10-06 00:19:21 +00:00
Chris Lattner
12274b9845 allow !strconcat to take more than two operands to eliminate 
!strconcat(!strconcat(!strconcat(!strconcat

Simplify some x86 td files to use it.

llvm-svn: 115719
 2010-10-05 23:58:18 +00:00
Chris Lattner
8365ab867e when david added support for #NAME# he didn't update the comments and 
tried (but failed) to artificially constrain it to working with #NAME#.
Just allow any # in identifiers, and update the comments.

llvm-svn: 115704
 2010-10-05 22:59:29 +00:00
Chris Lattner
3357066875 enhance tblgen to support anonymous defm's, use this to 
simplify the X86 CMOVmr's.

llvm-svn: 115702
 2010-10-05 22:51:56 +00:00
Jim Grosbach
f7e96a0110 trailing whitespace 
llvm-svn: 115664
 2010-10-05 20:35:57 +00:00
Sebastian Redl
6ee8773e0b Update attribute reading for the changed source location code. 
llvm-svn: 115624
 2010-10-05 15:59:36 +00:00
Douglas Gregor
9e6ce12abf Properly deserialize Clang types that are used as attribute arguments 
llvm-svn: 115616
 2010-10-05 14:51:48 +00:00
Sean Callanan
1cadd25316 Fixed the disassembler to handle two new X86 
instruction forms.  Now the ENTER instruction
disassembles correctly.

llvm-svn: 115573
 2010-10-04 22:45:51 +00:00
Francois Pichet
f1a8de98ab Fix typo 
llvm-svn: 115348
 2010-10-01 21:20:39 +00:00
Dale Johannesen
c14a1eda84 Massive rewrite of MMX: 
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243
 2010-09-30 23:57:10 +00:00
Jim Grosbach
046ae5dbac Let a target specify whether it wants an assembly printer to be the MC version 
or not. TableGen needs to generate the printInstruction() function as taking
an MCInstr* or a MachineInstr*, depending. Default to the old non-MC
version so that everything not yet using MC continues to just work without
fidding.

llvm-svn: 115126
 2010-09-30 01:29:54 +00:00
Evan Cheng
b44d480808 Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP 
pipeline forwarding path.

llvm-svn: 115098
 2010-09-29 22:42:35 +00:00
Jim Grosbach
7e54b358bd trailing whitespace 
llvm-svn: 115096
 2010-09-29 22:32:50 +00:00