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1185 Commits

Author SHA1 Message Date
Evan Cheng
bdf117bfac 80 col violation. 
llvm-svn: 74683
 2009-07-02 01:30:04 +00:00
Evan Cheng
d9f23ceeb9 Factor out ARM indexed load matching code. 
llvm-svn: 74681
 2009-07-02 01:23:32 +00:00
Bob Wilson
810a970c6f Add a new addressing mode for NEON load/store instructions. 
llvm-svn: 74658
 2009-07-01 23:16:05 +00:00
Bob Wilson
e3f8a640ac Fix a comment typo. 
llvm-svn: 74650
 2009-07-01 21:59:43 +00:00
Bob Wilson
11cddb5deb Fix up a comment: besides the >80col lines, the operation for this 
addressing mode is encoded in the second operand, not the third.

llvm-svn: 74641
 2009-07-01 21:22:45 +00:00
Bill Wendling
fdd5badace Update comments to make it clear that the function alignment is the Log2 of the 
bytes and not bytes.

llvm-svn: 74624
 2009-07-01 18:50:55 +00:00
Evan Cheng
37503e9671 Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. 
llvm-svn: 74580
 2009-07-01 01:59:31 +00:00
Daniel Dunbar
bc3d149e98 Remove unused AsmPrinter OptLevel argument, and propogate. 
- This more or less amounts to a revert of r65379. I'm curious to know what
   happened that caused this variable to become unused.

llvm-svn: 74579
 2009-07-01 01:48:54 +00:00
David Goodwin
19aa5c7d51 Add PIC load and store patterns for Thumb-2. 
llvm-svn: 74577
 2009-07-01 00:01:13 +00:00
David Goodwin
aa1f876954 Thumb-2 load and store double description. But nothing yet creates them. 
llvm-svn: 74566
 2009-06-30 22:50:01 +00:00
Bill Wendling
c0fb316bd3 Add an "alignment" field to the MachineFunction object. It makes more sense to 
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.

This allows for future work that would allow for precise no-op placement and the
like.

llvm-svn: 74564
 2009-06-30 22:38:32 +00:00
David Goodwin
5805e9aef5 Add thumb-2 store word, halfword, and byte. 
llvm-svn: 74555
 2009-06-30 22:11:34 +00:00
David Goodwin
aad223dd8a Improve Thumb-2 jump table support. 
llvm-svn: 74549
 2009-06-30 19:50:22 +00:00
David Goodwin
5545d82866 Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table. 
llvm-svn: 74543
 2009-06-30 18:04:13 +00:00
Evan Cheng
2a527c3419 A few more load instructions. 
llvm-svn: 74500
 2009-06-30 02:15:48 +00:00
David Goodwin
4f53387d26 Add Thumb-2 support for TEQ amd TST. 
llvm-svn: 74468
 2009-06-29 22:49:42 +00:00
David Goodwin
9e1280adf3 Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. 
llvm-svn: 74423
 2009-06-29 15:33:01 +00:00
Duncan Sands
660e9c2106 Include the new file ThumbRegisterInfo.cpp to CMakeLists.txt 
to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.

llvm-svn: 74421
 2009-06-29 13:11:32 +00:00
Evan Cheng
093adf3ff9 Implement Thumb2 ldr. 
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420
 2009-06-29 07:51:04 +00:00
Anton Korobeynikov
7231e149ef Simplify a bit 
llvm-svn: 74385
 2009-06-27 12:59:03 +00:00
Anton Korobeynikov
1db77899c1 ARM refactoring. Step 2: split RegisterInfo 
llvm-svn: 74384
 2009-06-27 12:16:40 +00:00
Douglas Gregor
6ee152cc94 Add ThumbInstrInfo.cpp to the CMake makefiles 
llvm-svn: 74382
 2009-06-27 07:44:59 +00:00
Evan Cheng
817712377a Renaming for consistency. 
llvm-svn: 74368
 2009-06-27 02:26:13 +00:00
David Goodwin
e1979dfbf5 Remove outdated comment. 
llvm-svn: 74357
 2009-06-26 23:39:02 +00:00
David Goodwin
90fc344e41 When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not. 
llvm-svn: 74355
 2009-06-26 23:13:13 +00:00
Anton Korobeynikov
aab56476b2 Split thumb-related stuff into separate classes. 
Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329
 2009-06-26 21:28:53 +00:00
David Goodwin
921faa64cd Thumb-2 has CLZ. 
llvm-svn: 74322
 2009-06-26 20:47:43 +00:00
David Goodwin
9da977f216 Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc". 
llvm-svn: 74321
 2009-06-26 20:45:56 +00:00
David Goodwin
46eb5a7a2d ADC used to implement adde should use "adcs" opcode instead of "adc". 
llvm-svn: 74293
 2009-06-26 18:07:25 +00:00
David Goodwin
877790aa5f Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI. 
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.

llvm-svn: 74288
 2009-06-26 16:10:07 +00:00
Evan Cheng
b93625f89e Simplify predicate CarryDefIsUsed. 
llvm-svn: 74277
 2009-06-26 06:10:18 +00:00
Devang Patel
a7a5664fbb Let's ignore MDStrings also! 
llvm-svn: 74255
 2009-06-26 02:26:12 +00:00
Evan Cheng
2eb1525e2a Add a note about commuting conditional move. 
llvm-svn: 74241
 2009-06-26 00:28:48 +00:00
Evan Cheng
f23c8a5c8a These are done / no longer applicable. 
llvm-svn: 74239
 2009-06-26 00:25:27 +00:00
Evan Cheng
4f0e461e97 Mark a bunch of instructions commutable. 
llvm-svn: 74237
 2009-06-26 00:19:44 +00:00
Evan Cheng
e45355b804 tst is also commutable. 
llvm-svn: 74236
 2009-06-26 00:19:07 +00:00
Evan Cheng
4ac765118d Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. 
llvm-svn: 74228
 2009-06-25 23:34:10 +00:00
David Goodwin
74414108e9 Use MVN for ~t2_so_imm immediates. 
llvm-svn: 74223
 2009-06-25 23:11:21 +00:00
David Goodwin
a0ed5f6847 Add Def/Use of CPSR for Thumb-1 instructions. 
llvm-svn: 74219
 2009-06-25 22:49:55 +00:00
Evan Cheng
331e7cc684 Unbreak mingw build. Patch by Viktor Kutuzov. 
llvm-svn: 74212
 2009-06-25 22:04:44 +00:00
Evan Cheng
0cced3daa8 ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS. 
llvm-svn: 74200
 2009-06-25 20:59:23 +00:00
David Goodwin
c72bad36d7 Test commit 
llvm-svn: 74185
 2009-06-25 17:52:32 +00:00
Bob Wilson
38779c951a Revert 74164. We'll want to use this method later. 
llvm-svn: 74176
 2009-06-25 16:03:07 +00:00
Bob Wilson
ef8fd818bf Remove unused hasV6T2Ops method. We already have a separate feature to 
identify Thumb2.

llvm-svn: 74164
 2009-06-25 05:20:31 +00:00
Douglas Gregor
7841f61ced Add missing dependencies to the CMake build system. 
llvm-svn: 74161
 2009-06-25 05:03:06 +00:00
Evan Cheng
a3be8cba60 Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag. 
llvm-svn: 74158
 2009-06-25 02:08:06 +00:00
Evan Cheng
e31583bf2a Add thumb2 add sp. 
llvm-svn: 74156
 2009-06-25 01:21:30 +00:00
Evan Cheng
8e61610960 Some reorg and additional comments. 
llvm-svn: 74152
 2009-06-25 01:05:06 +00:00
Devang Patel
d98b076409 No need to code gen MDNodes 
llvm-svn: 74150
 2009-06-25 00:47:42 +00:00
Evan Cheng
e8c58ee743 Add Thumb2 pc relative add. 
llvm-svn: 74141
 2009-06-24 23:47:58 +00:00
Evan Cheng
32695e2413 80 col violation. 
llvm-svn: 74138
 2009-06-24 23:14:45 +00:00
Chris Lattner
d59a5b9f8b sink dwarf finalization out of each target into AsmPrinter::doFinalization 
llvm-svn: 74097
 2009-06-24 18:54:37 +00:00
Chris Lattner
0690755320 eliminate the ExtWeakSymbols set from AsmPrinter. This eliminates 
a bunch of code from all the targets, and eliminates nondeterministic
ordering of directives being emitted in the output.

llvm-svn: 74096
 2009-06-24 18:52:01 +00:00
Nick Lewycky
68273b013b Unbreak build on Linux by removing Darwinism. 
llvm-svn: 74046
 2009-06-24 01:08:42 +00:00
Dan Gohman
661e8b54fa Revert this accidental commit. 
llvm-svn: 74042
 2009-06-24 00:55:55 +00:00
Dan Gohman
3bf5d76081 Move the special cases for constants out of getUnknown and into 
createSCEV. Also, recognize UndefValue in createSCEV.

Change getIntegerSCEV's comment to avoid mentioning FP types,
and re-implement it in terms of getConstant instead of getUnknown.

llvm-svn: 74041
 2009-06-24 00:54:57 +00:00
Bob Wilson
7bd642b80c Provide InitializeAllTargets and InitializeNativeTarget functions in the 
C bindings.  Change all the backend "Initialize" functions to have C linkage.
Change the "llvm/Config/Targets.def" header to use C-style comments to avoid
compile warnings.

llvm-svn: 74026
 2009-06-23 23:59:40 +00:00
Evan Cheng
4dcc3bd23b Test instructions operands were printed in the wrong order. 
llvm-svn: 73990
 2009-06-23 19:56:37 +00:00
Evan Cheng
eaad82627b Proper patterns for thumb2 shift and rotate instructions. 
llvm-svn: 73987
 2009-06-23 19:39:13 +00:00
Evan Cheng
4fc8a75ae1 Code clean up. 
llvm-svn: 73986
 2009-06-23 19:38:34 +00:00
Evan Cheng
1333ee8eb6 Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available. 
llvm-svn: 73985
 2009-06-23 19:38:13 +00:00
Evan Cheng
b7077f2943 Rename SelectShifterOperand to SelectThumb2ShifterOperandReg. 
llvm-svn: 73975
 2009-06-23 18:14:38 +00:00
Douglas Gregor
3ca1e68417 Eliminate object-relinking support from CMake. Fixes PR 4429 and 
cleans up the CMake-based build system a bit. Started by a patch from
Xerxes Rånby.

llvm-svn: 73969
 2009-06-23 17:57:35 +00:00
Evan Cheng
73e4b03dc8 Obvious typo. 
llvm-svn: 73967
 2009-06-23 17:54:26 +00:00
Evan Cheng
3e8033f7f7 Initial Thumb2 support. Majority of the work is done by David Goodwin. There are 
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.

I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.

Test cases will be contributed later after I re-organize what's in svn first.

llvm-svn: 73965
 2009-06-23 17:48:47 +00:00
Evan Cheng
e950c375ea Minor reorg. 
llvm-svn: 73948
 2009-06-23 05:25:29 +00:00
Evan Cheng
92a49d75e4 Replace isTwoAddress with operand constraint. 
llvm-svn: 73947
 2009-06-23 05:23:49 +00:00
Bob Wilson
6db76aaf10 Add support for ARM's Advanced SIMD (NEON) instruction set. 
This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919
 2009-06-22 23:27:02 +00:00
Bob Wilson
48de87abcb Add explicit types for shift count constants. This is in preparation for 
another change that makes the types ambiguous (at least as far as tablegen
is concerned).

llvm-svn: 73909
 2009-06-22 22:08:29 +00:00
Bob Wilson
6e81f12950 Use thumb2 for ARM architectures V6T2 and later. Fix a bug in checking 
for "thumb" and add a check for V6T2.

llvm-svn: 73905
 2009-06-22 21:28:22 +00:00
Bob Wilson
0c2c5f65e2 For Darwin on ARMv6 and newer, make register r9 available for use as a 
caller-saved register.

llvm-svn: 73901
 2009-06-22 21:01:46 +00:00
Evan Cheng
b37e7e24d0 hasFP should return true if frame address is taken. 
llvm-svn: 73893
 2009-06-22 18:38:48 +00:00
Bob Wilson
c859e1c6bb Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops 
predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.

llvm-svn: 73887
 2009-06-22 17:29:13 +00:00
Devang Patel
a011b501a0 Remove unused field. 
llvm-svn: 73815
 2009-06-20 01:07:54 +00:00
Evan Cheng
f18de63563 Enable arm pre-allocation load / store multiple optimization pass. 
llvm-svn: 73791
 2009-06-19 23:17:27 +00:00
Devang Patel
35810cd07b Move up dwarf writer initialization in common AsmPrinter class. 
llvm-svn: 73784
 2009-06-19 21:54:26 +00:00
Evan Cheng
706927c96a Add comments. 
llvm-svn: 73761
 2009-06-19 07:06:07 +00:00
Evan Cheng
8f613095de Should be using Bcc (average) latency to determine if-conversion threshold, not BL. 
llvm-svn: 73759
 2009-06-19 06:56:26 +00:00
Evan Cheng
667924dc46 Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr. 
llvm-svn: 73749
 2009-06-19 01:59:04 +00:00
Evan Cheng
f671ce4eba Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. 
llvm-svn: 73747
 2009-06-19 01:51:50 +00:00
Eli Friedman
003abaa60d Mark a few Thumb instructions commutable; just happened to spot this 
while experimenting.  I'm reasonably sure this is correct, but please 
tell me if these instructions have some strange property which makes this
change unsafe.

llvm-svn: 73746
 2009-06-19 01:43:08 +00:00
Chris Lattner
c2b0fd0304 merge the common darwin settings from the X86/PPC/ARM targets 
into DarwinTargetAsmInfo.cpp.  The remaining differences should
be evaluated.  It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.

llvm-svn: 73742
 2009-06-19 00:08:39 +00:00
Chris Lattner
6cd267dcc5 move mangler quote handling from asm printers to TargetAsmInfo. 
llvm-svn: 73738
 2009-06-18 23:41:35 +00:00
Chris Lattner
ea0ea2f4bc simplify macro debug info directive handling. 
llvm-svn: 73736
 2009-06-18 23:31:37 +00:00
Evan Cheng
7426d278ae Remove UseThumbBacktraces. Just check if subtarget is darwin. 
llvm-svn: 73734
 2009-06-18 23:14:30 +00:00
Evan Cheng
6c1c55f942 On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body. 
llvm-svn: 73720
 2009-06-18 20:37:15 +00:00
Evan Cheng
82a8ab8a8e - Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints. 
- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.

llvm-svn: 73671
 2009-06-18 02:04:01 +00:00
Bob Wilson
1866500851 ARM unified syntax is not specific to ELF; use it for Darwin, too. 
llvm-svn: 73665
 2009-06-18 00:36:17 +00:00
Anton Korobeynikov
dbb79a8409 Fix asm string from MOVi16 
llvm-svn: 73661
 2009-06-17 23:43:36 +00:00
Anton Korobeynikov
4e0c3634cc Thumb2 instructions are enabled only in unified assembler mode. 
Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.

llvm-svn: 73660
 2009-06-17 23:43:18 +00:00
Anton Korobeynikov
7fd29c57a8 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

llvm-svn: 73622
 2009-06-17 18:13:58 +00:00
Douglas Gregor
f5291553f2 Introduce new headers whose inclusion forces linking and 
initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.

llvm-svn: 73543
 2009-06-16 20:12:29 +00:00
Anton Korobeynikov
cc8d0058e2 Address review comments: add 3 ARM calling conventions. 
Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.

llvm-svn: 73530
 2009-06-16 18:50:49 +00:00
Anton Korobeynikov
a74b8323d0 GNU as refuses to assemble "pop {}" instruction. Do not emit such 
(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

llvm-svn: 73529
 2009-06-16 18:49:08 +00:00
Evan Cheng
b89602d382 On Darwin, frame pointer r7 is never available. 
llvm-svn: 73434
 2009-06-15 22:32:01 +00:00
Anton Korobeynikov
2670a363da Rename methods for the sake of consistency. 
llvm-svn: 73428
 2009-06-15 21:46:20 +00:00
Evan Cheng
c007d30aad Typo. 
llvm-svn: 73422
 2009-06-15 21:18:20 +00:00
Evan Cheng
659d2536b8 Do not form ldrd / strd if the two dests / srcs are the same. Code clean up. 
llvm-svn: 73413
 2009-06-15 20:54:56 +00:00
Evan Cheng
9c5f793659 Silence a warning. 
llvm-svn: 73406
 2009-06-15 19:36:32 +00:00
Evan Cheng
3219c7fbe5 Part 1. 
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381
 2009-06-15 08:28:29 +00:00
Evan Cheng
d0a66e438f Add a ARM specific pre-allocation pass that re-schedule loads / stores from 
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291
 2009-06-13 09:12:55 +00:00
Evan Cheng
2f784781aa Mark some pattern-less instructions as neverHasSideEffects. 
llvm-svn: 73252
 2009-06-12 20:46:18 +00:00
Anton Korobeynikov
6dbf7b689c Typo 
llvm-svn: 73098
 2009-06-08 22:59:50 +00:00
Anton Korobeynikov
0677cee20d Revert hunk commited by accident 
llvm-svn: 73097
 2009-06-08 22:57:18 +00:00
Anton Korobeynikov
d08df21f36 The attached patches implement most of the ARM AAPCS-VFP hard float 
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

llvm-svn: 73095
 2009-06-08 22:53:56 +00:00
Anton Korobeynikov
52b2898854 Separate V6 from V6T2 since the latter has some extra nice instructions 
llvm-svn: 73085
 2009-06-08 21:20:36 +00:00
Anton Korobeynikov
7e9e1b3e1f Add helper for checking of Thumb1 mode 
llvm-svn: 73080
 2009-06-08 20:31:02 +00:00
Dan Gohman
e0d593cbf6 Add explicit keywords. 
llvm-svn: 72969
 2009-06-05 23:05:51 +00:00
Evan Cheng
ea31ec569b Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then. 
llvm-svn: 72955
 2009-06-05 19:08:58 +00:00
Evan Cheng
35a504c6e9 When merging multiple load / store instructions. Use the DebugLoc of the first one. 
llvm-svn: 72952
 2009-06-05 18:19:23 +00:00
Evan Cheng
d240854a82 Code clean up: return vector by reference rather than by value. No functionality changes. 
llvm-svn: 72950
 2009-06-05 17:56:14 +00:00
Dan Gohman
ee407d25ca Remove some unnecessary #includes. 
llvm-svn: 72948
 2009-06-05 16:32:58 +00:00
Evan Cheng
e3a05e6690 Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface. 
llvm-svn: 72826
 2009-06-04 01:15:28 +00:00
Evan Cheng
82f8fa333e Temporarily revert 72756 for now. 
llvm-svn: 72757
 2009-06-03 07:40:47 +00:00
Evan Cheng
5afbef29fa Fold preceding / trailing base inc / dec into the single load / store as well. 
llvm-svn: 72756
 2009-06-03 06:14:58 +00:00
Anton Korobeynikov
e7e9118514 Implement review feedback. Make thumb2 'normal' subtarget feature 
llvm-svn: 72698
 2009-06-01 20:00:48 +00:00
Bruno Cardoso Lopes
7765059062 Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray 
llvm-svn: 72697
 2009-06-01 19:57:37 +00:00
Anton Korobeynikov
f6ec078b26 Do not emit "generic" CPU string. This fixes PR4291. 
llvm-svn: 72696
 2009-06-01 19:03:17 +00:00
Bruno Cardoso Lopes
4da7e7af43 First patch in the direction of splitting MachineCodeEmitter in two subclasses: 
JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray

llvm-svn: 72631
 2009-05-30 20:51:52 +00:00
Bill Wendling
8235a05c1a Untabification. 
llvm-svn: 72604
 2009-05-30 01:09:53 +00:00
Anton Korobeynikov
4f5b1ef545 Add placeholder for thumb2 stuff 
llvm-svn: 72593
 2009-05-29 23:41:08 +00:00
Chris Lattner
10cac1a776 fix typo 
llvm-svn: 72395
 2009-05-25 19:51:07 +00:00
Anton Korobeynikov
1fe3d6d47b Add ARMv7 architecture, Cortex processors and different FPU modes handling. 
llvm-svn: 72337
 2009-05-23 19:51:43 +00:00
Anton Korobeynikov
c16f747585 Emit ARM Build Attributes 
llvm-svn: 72336
 2009-05-23 19:51:20 +00:00
Anton Korobeynikov
34fc85e2ee Propagate CPU string out of SubtargetFeatures 
llvm-svn: 72335
 2009-05-23 19:50:50 +00:00
Bob Wilson
372984e7a2 Only 64-bit targets support TImode libcalls. Disable the TImode shift libcalls 
for ARM.  This fixes rdar://6908807.

llvm-svn: 72269
 2009-05-22 17:38:41 +00:00
Bob Wilson
0ac9317588 Minor formatting fixes. 
llvm-svn: 72172
 2009-05-20 16:30:25 +00:00
Bob Wilson
ba6b02b54b Fix pr4227: Handle large immediate values in inline assembly. 
llvm-svn: 72138
 2009-05-19 21:27:57 +00:00
Bob Wilson
5e7a2b4ff8 Follow up on new support for memory operands in ARM inline assembly. 
This fixes pr4233.

llvm-svn: 72115
 2009-05-19 18:33:02 +00:00
Bob Wilson
c6726ecca5 Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and 
the stack.  Patch by Sandeep Patel.

llvm-svn: 72106
 2009-05-19 10:02:36 +00:00
Bob Wilson
ec676a76e7 Fix pr4091: Add support for "m" constraint in ARM inline assembly. 
llvm-svn: 72105
 2009-05-19 05:53:42 +00:00
Bob Wilson
51e9d81e72 Fix pr4202: Disable CodePlacementOpt for ARM. The ARMConstantIslandPass has 
to run last because it needs to know the exact size and position of every
basic block.  Currently CodePlacementOpt is set up to run last.  It might be
worthwhile to investigate reordering these passes, but for now, let's just
make it work.

llvm-svn: 72037
 2009-05-18 20:55:32 +00:00
Jim Grosbach
bed3aeff20 Update the names of the exception handling sjlj instrinsics to 
llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).

llvm-svn: 71758
 2009-05-14 00:46:35 +00:00
Jim Grosbach
024feec42e Spelling correction s/builting/builtin/ and remove trailing whitespace in a few places 
llvm-svn: 71735
 2009-05-13 22:32:43 +00:00
Evan Cheng
9bd08f0cde Run code placement optimization for targets that want it (arm and x86 for now). 
llvm-svn: 71726
 2009-05-13 21:42:09 +00:00
Bill Wendling
e421c8f63d Change MachineInstrBuilder::addReg() to take a flag instead of a list of 
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).

llvm-svn: 71722
 2009-05-13 21:33:08 +00:00
Jim Grosbach
4bb5e9d1df Add support for GCC compatible builtin setjmp and longjmp intrinsics. This is 
a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.

llvm-svn: 71610
 2009-05-12 23:59:14 +00:00
Jim Grosbach
4861b683a8 correct register class for tADDspi to GPR since the register will always be SP 
llvm-svn: 71602
 2009-05-12 22:30:18 +00:00
Bob Wilson
5a9381d75f Fix up a few minor typos in comments. 
llvm-svn: 71563
 2009-05-12 17:35:29 +00:00
Bob Wilson
de6e2f9bf0 Fix 80-col violations and remove trailing whitespace. No functional changes. 
llvm-svn: 71562
 2009-05-12 17:09:30 +00:00
Duncan Sands
f7af13b2d4 Rename PaddedSize to AllocSize, in the hope that this 
will make it more obvious what it represents, and stop
it being confused with the StoreSize.

llvm-svn: 71349
 2009-05-09 07:06:46 +00:00
Bill Wendling
40a162f75f Instead of passing in an unsigned value for the optimization level, use an enum, 
which better identifies what the optimization is doing. And is more flexible for
future uses.

llvm-svn: 70440
 2009-04-29 23:29:43 +00:00
Bill Wendling
7546bed590 Second attempt: 
Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.

llvm-svn: 70343
 2009-04-29 00:15:41 +00:00
Bill Wendling
ef47ace92f r70270 isn't ready yet. Back this out. Sorry for the noise. 
llvm-svn: 70275
 2009-04-28 01:04:53 +00:00
Bill Wendling
2799e916c3 Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to 
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...

llvm-svn: 70270
 2009-04-28 00:21:31 +00:00
Bob Wilson
162870a4b3 Change LowerCallResult method so that CCValAssign::BCvt can be used with 
f64 types.  This is not used for anything yet.

llvm-svn: 70006
 2009-04-25 00:33:20 +00:00
Bob Wilson
0ac8a0cf95 Adjust a comment to reflect what the code does. Splitting a 64-bit argument 
between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.

llvm-svn: 69978
 2009-04-24 17:05:01 +00:00
Bob Wilson
2a47f01759 Fix up some problems with getCopyToReg and getCopyFromReg nodes being 
chained and "flagged" together.  I also made a few changes to handle the
chain and flag values more consistently.  I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).

llvm-svn: 69977
 2009-04-24 17:00:36 +00:00
Bob Wilson
1067abd956 Remove unnecessary references to f32 types. After specifying that f32 
should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.

llvm-svn: 69973
 2009-04-24 16:55:25 +00:00
Bob Wilson
f7e9ff1d28 Move duplicated AddLiveIn function from X86 and ARM backends to be a method 
in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock.  Thanks for Anton for suggesting this.

llvm-svn: 69615
 2009-04-20 18:36:57 +00:00