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Commit Graph

708 Commits

Author SHA1 Message Date
Tom Stellard
988925aeae R600/SI: Expand all v8[if]32 operations
llvm-svn: 201371
2014-02-13 23:34:15 +00:00
Tom Stellard
309a624102 R600/SI: Add a pattern for i32 anyext
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 201370
2014-02-13 23:34:13 +00:00
Tom Stellard
4b0c3551df R600/SI: Completely Disable TypeRewriter on compute
llvm-svn: 201369
2014-02-13 23:34:12 +00:00
Tom Stellard
4447febe55 R600/SI: Split global vector loads with more than 4 elements
llvm-svn: 201368
2014-02-13 23:34:10 +00:00
Benjamin Kramer
b51d0de00f R600: Always implement both versions of isTruncateFree and add a sanity check.
llvm-svn: 201222
2014-02-12 10:17:54 +00:00
Matt Arsenault
cc13cc04ab R600/SI: Fix assertion on infinite loops.
This isn't the most useful case to fix in the real world,
but bugpoint runs into this.

llvm-svn: 201177
2014-02-11 21:12:38 +00:00
Matt Arsenault
38609a2ae1 R600: Implement isTruncateFree
Truncation is just accessing a subregister for any multiple of
the register size, so it's free.

llvm-svn: 201107
2014-02-10 19:57:42 +00:00
Tom Stellard
2712f90019 R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used
DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0.  When M0 is uninitialized,
then we experience undefined behavior.

This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.

llvm-svn: 201097
2014-02-10 16:58:30 +00:00
Tom Stellard
de54e7d923 R600/SI: Only use S_WQM_B64 in pixel shaders
This doesn't change any functionality, since we only have two shader
types (compute and pixel) that use local memory.  We're just changing
the logic to match the documentation.

llvm-svn: 201096
2014-02-10 16:58:27 +00:00
Tom Stellard
1906c48d55 R600/SI: Add a MUBUF store pattern for Reg+Imm offsets
llvm-svn: 200935
2014-02-06 18:36:41 +00:00
Tom Stellard
c690406420 R600/SI: Add a MUBUF store pattern for Imm offsets
llvm-svn: 200934
2014-02-06 18:36:39 +00:00
Tom Stellard
2e3a1cc4d8 R600/SI: Add a MUBUF load pattern for Reg+Imm offsets
llvm-svn: 200933
2014-02-06 18:36:38 +00:00
Tom Stellard
879ab71511 R600/SI: Use immediates offsets for SMRD instructions whenever possible
There was a problem with the old pattern, so we were copying some
larger immediates into registers when we could have been encoding
them in the instruction.

llvm-svn: 200932
2014-02-06 18:36:34 +00:00
Matt Arsenault
7b69102edb Add address space argument to allowsUnalignedMemoryAccess.
On R600, some address spaces have more strict alignment
requirements than others.

llvm-svn: 200887
2014-02-05 23:15:53 +00:00
Michel Danzer
ed3052cc54 R600/SI: Add pattern for zero-extending i1 to i32
Fixes opencl-example if_* tests with radeonsi.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200830
2014-02-05 09:48:05 +00:00
Duncan P. N. Exon Smith
7024ad6965 cleanup: scc_iterator consumers should use isAtEnd
No functional change.  Updated loops from:

    for (I = scc_begin(), E = scc_end(); I != E; ++I)

to:

    for (I = scc_begin(); !I.isAtEnd(); ++I)

for teh win.

llvm-svn: 200789
2014-02-04 19:19:07 +00:00
Rafael Espindola
34d0e998bd Every target uses .align. Simplify.
llvm-svn: 200782
2014-02-04 18:39:51 +00:00
Tom Stellard
d35a25ea14 R600/SI: Expand i1 BR_CC
This fixes a crashes in the OpenCV test suite and also the scrypt
kernel in bfgminer.

I was unable to come up with a reduced test case for this.

https://bugs.freedesktop.org/show_bug.cgi?id=72785

llvm-svn: 200776
2014-02-04 17:18:43 +00:00
Tom Stellard
f57fbab65b R600/SI: Don't assume copies will be coalesced in SIFixSGPRCopies
There is no lit test for this, because it would be too big and
complicated, but it does fix a crash in the Arithm/Absdiff.* OpenCV test.

llvm-svn: 200775
2014-02-04 17:18:42 +00:00
Tom Stellard
279daf2506 R600/SI: Custom lower i64 ISD::SELECT
llvm-svn: 200774
2014-02-04 17:18:40 +00:00
Tom Stellard
f4a180e50b R600: Enable vector fpow.
The OpenCL specs say: "The vector versions of the math functions operate
component-wise. The description is per-component."

Patch by: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 200773
2014-02-04 17:18:37 +00:00
Michel Danzer
292dfb1151 R600/SI: Fix fneg for 0.0
V_ADD_F32 with source modifier does not produce -0.0 for this. Just
manipulate the sign bit directly instead.

Also add a pattern for (fneg (fabs ...)).

Fixes a bunch of bit encoding piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200743
2014-02-04 07:12:38 +00:00
Matt Arsenault
32dd3cc196 Add DEBUG_TYPE to SIAnnotateControlFlow
llvm-svn: 200720
2014-02-03 22:58:05 +00:00
Matt Arsenault
4198d962c0 R600/SI: Fix insertelement with dynamic indices.
This didn't work for any integer vectors, and didn't
work with some sizes of float vectors. This should now
work with all sizes of float and i32 vectors.

llvm-svn: 200619
2014-02-02 00:05:35 +00:00
Rafael Espindola
9e0d89fd92 Remove the last hasRawTextSupport call from R600.
There is nothing wrong with printing the disassembly section when printing
text. An hypothetical assembler would then produce a .o just like our
direct object emission produces.

llvm-svn: 200583
2014-01-31 22:14:06 +00:00
Rafael Espindola
181d98005b Replace another use with hasRawTextSupport+EmitRawText with emitRawComment.
llvm-svn: 200582
2014-01-31 22:08:19 +00:00
Rafael Espindola
7a4c0f827a Use emitRawComment to avoid a call to hasRawTextSupport.
llvm-svn: 200581
2014-01-31 21:54:49 +00:00
David Woodhouse
6c8fefd999 Delete MCSubtargetInfo data members from target MCCodeEmitter classes
The subtarget info is explicitly passed to the EncodeInstruction
method and we should use that subtarget info to influence any
encoding decisions.

llvm-svn: 200350
2014-01-28 23:13:25 +00:00
David Woodhouse
a79a37b435 Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()
llvm-svn: 200349
2014-01-28 23:13:18 +00:00
David Woodhouse
4a4c611e36 Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()
llvm-svn: 200348
2014-01-28 23:13:07 +00:00
David Woodhouse
5d0b529d58 Change MCStreamer EmitInstruction interface to take subtarget info
llvm-svn: 200345
2014-01-28 23:12:42 +00:00
Michel Danzer
71542b5f92 R600/SI: Add pattern for truncating i32 to i1
Fixes half a dozen piglit tests with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200283
2014-01-28 03:01:16 +00:00
Michel Danzer
65a5397c22 R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200196
2014-01-27 07:20:51 +00:00
Michel Danzer
36dd8ac577 R600/SI: Add intrinsic for S_SENDMSG instruction
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 200195
2014-01-27 07:20:44 +00:00
Rafael Espindola
c1b8f12d60 Add back spaces I missed in the conversion to emitRawComments.
Sorry about that.

llvm-svn: 200171
2014-01-27 00:19:41 +00:00
Rafael Espindola
7ee6a0aa63 Use emitRawComment instead of EmitRawText.
llvm-svn: 200170
2014-01-27 00:16:00 +00:00
Rafael Espindola
bfdd58b802 Pass a MCSubtargetInfo down to the TargetStreamer creation.
With this the target streamers will be able to know the target features that
are in use.

llvm-svn: 200135
2014-01-26 06:38:58 +00:00
Rafael Espindola
806f778fa0 Construct the MCStreamer before constructing the MCTargetStreamer.
This has a few advantages:
* Only targets that use a MCTargetStreamer have to worry about it.
* There is never a MCTargetStreamer without a MCStreamer, so we can use a
  reference.
* A MCTargetStreamer can talk to the MCStreamer in its constructor.

llvm-svn: 200129
2014-01-26 06:06:37 +00:00
Juergen Ributzka
e4d29eb495 Add final and owerride keywords to TargetTransformInfo's subclasses.
llvm-svn: 200021
2014-01-24 18:22:59 +00:00
Alp Toker
1c4b33e8e5 Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

llvm-svn: 200018
2014-01-24 17:20:08 +00:00
Tom Stellard
58d7c4cc96 R600: Remove successive JUMP in AnalyzeBranch when AllowModify is true
This fixes a crash in the OpenCV OpenCL test suite.

There is no lit test for this, because the test would be very large
and could easily be invalidated by changes to the scheduler
or other parts of the compiler.

Patch by:  Vincent Lejeune

llvm-svn: 199919
2014-01-23 18:49:34 +00:00
Tom Stellard
e8c59f575b R600: Disable the BFE pattern
This pattern uses an SDNodeXForm, which isn't being emitted for some
reason.  I can get it to work by attaching the PatLeaf that has the
XForm to the argument in the output pattern, but this results in an
immediate being used in a register operand, which the backend can't
handle yet.

llvm-svn: 199918
2014-01-23 18:49:33 +00:00
Tom Stellard
25fa3e2b1d R600: Correctly handle vertex fetch clauses the precede ENDIFs
The control flow finalizer would sometimes use an ALU_POP_AFTER
instruction before the vetex fetch clause instead of using a POP
instruction after it.

llvm-svn: 199917
2014-01-23 18:49:31 +00:00
Tom Stellard
ab9b18423b R600: Unconditionally unroll loops that contain GEPs with alloca pointers
Implement the getUnrollingPreferences() function for
AMDGPUTargetTransformInfo so that loops that do address calculations
on pointers derived from alloca are unconditionally unrolled.

Unrolling these loops makes it more likely that SROA will be able to
eliminate the allocas, which is a big win for R600 since memory
allocated by alloca (private memory) is really slow.

llvm-svn: 199916
2014-01-23 18:49:28 +00:00
Tom Stellard
6f13c22a7a R600: Recommit 199842: Add work-around for the CF stack entry HW bug
The unit test is now disabled on non-asserts builds.

The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE,
CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of
sub-entries on the stack is greater than or equal to the stack entry
size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is
present when number of sub-entries module 8 is either 7 or 0)

We choose to be conservative and always apply the work-around when the
number of sub-enries is greater than or equal to the stack entry size,
so that we can safely over-allocate the stack when we are unsure of the
stack allocation rules.

reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199905
2014-01-23 16:18:02 +00:00
Tom Stellard
d5181ee67d Revert "R600: Add work-around for the CF stack entry HW bug"
This reverts commit 35b8331cad6eb512a2506adbc394201181da94ba.

The -debug-only flag for llc doesn't appear to be available in
all build configurations.

llvm-svn: 199845
2014-01-22 22:20:54 +00:00
Tom Stellard
cd874ab98c R600: Add work-around for the CF stack entry HW bug
The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE,
CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of
sub-entries on the stack is greater than or equal to the stack entry
size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is
present when number of sub-entries module 8 is either 7 or 0)

We choose to be conservative and always apply the work-around when the
number of sub-enries is greater than or equal to the stack entry size,
so that we can safely over-allocate the stack when we are unsure of the
stack allocation rules.

reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199842
2014-01-22 21:55:46 +00:00
Tom Stellard
6cc70339a1 R600: Add some missing CF instruction definitions to the .td files.
reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199841
2014-01-22 21:55:44 +00:00
Tom Stellard
ae477cc774 R600: Refactor stack size calculation
reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199840
2014-01-22 21:55:43 +00:00
Tom Stellard
2569ec88de R600: CF_PUSH is the same on Evergreen and Cayman
reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 199839
2014-01-22 21:55:41 +00:00