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6998 Commits

Author SHA1 Message Date
Evan Cheng
44488cb676 Implement inline asm modifier P. 
llvm-svn: 35640
 2007-04-04 00:13:29 +00:00
Evan Cheng
d5956e4409 Typo. 
llvm-svn: 35639
 2007-04-04 00:06:07 +00:00
Bill Wendling
a4aa65bc38 Adding more MMX instructions. 
llvm-svn: 35638
 2007-04-03 23:48:32 +00:00
Chris Lattner
78271f0596 make a new missing features section 
llvm-svn: 35637
 2007-04-03 23:41:34 +00:00
Evan Cheng
2cd9df6983 Remove unused constant pool entries. 
llvm-svn: 35635
 2007-04-03 23:39:48 +00:00
Bill Wendling
ff2c460267 Updated 
llvm-svn: 35634
 2007-04-03 23:37:20 +00:00
Evan Cheng
db15aa24f9 Fixed a bug that causes codegen of noop like add r0, r0, #0. 
llvm-svn: 35627
 2007-04-03 21:31:21 +00:00
Nicolas Geoffray
681a87d9e8 Starting implementation of the ELF32 ABI specification of varargs handling. 
LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.

llvm-svn: 35625
 2007-04-03 13:59:52 +00:00
Nicolas Geoffray
5897c064a6 The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules 
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.

llvm-svn: 35624
 2007-04-03 12:35:28 +00:00
Nicolas Geoffray
45c3620d12 Addition to the previous commit for getCalleeSavedRegClasses: 
"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."

llvm-svn: 35623
 2007-04-03 10:57:49 +00:00
Nicolas Geoffray
b7c0895529 The ELF ABI specifies F1-F8 registers as argument registers for double, not 
F1-F10. This affects only ELF, not MachO.

llvm-svn: 35622
 2007-04-03 10:27:07 +00:00
Evan Cheng
16696f0ad8 Inverted logic. 
llvm-svn: 35619
 2007-04-03 06:44:25 +00:00
Bill Wendling
a2eabd50c0 Changed to new MMX_ recipes. 
llvm-svn: 35617
 2007-04-03 06:18:31 +00:00
Bill Wendling
ca2124e5a9 Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them. 
llvm-svn: 35616
 2007-04-03 06:00:37 +00:00
Chris Lattner
4d702a890c Arm supports negative strides as well, add them. This lets us compile: 
CodeGen/ARM/arm-negative-stride.ll to:

LBB1_2: @bb
        str r1, [r3, -r0, lsl #2]
        add r0, r0, #1
        cmp r0, r2
        bne LBB1_2      @bb

llvm-svn: 35609
 2007-04-03 00:13:57 +00:00
Dale Johannesen
e1c3dc7c78 fix off by 1 error in displacement computation 
llvm-svn: 35602
 2007-04-02 20:31:06 +00:00
Chris Lattner
726d461daf fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales 
to be folded into non-store instructions.

llvm-svn: 35601
 2007-04-02 18:51:18 +00:00
Chris Lattner
ff9caac83e add support for the 'w' inline asm register class. 
llvm-svn: 35598
 2007-04-02 17:24:08 +00:00
Chris Lattner
dbce9ef4b8 Fix a bug which caused us to never be able to use signed comparisons for 
equality comparisons of a constant.  This allows us to codegen the 'sintzero'
loop in PR1288 as:

LBB1_1: ;cond_next
        li r4, 0
        addi r2, r2, 1
        stw r4, 0(r3)
        addi r3, r3, 4
        cmpwi cr0, r2, -1
        bne cr0, LBB1_1 ;cond_next

instead of:

LBB1_1: ;cond_next
        addi r2, r2, 1
        li r4, 0
        xoris r5, r2, 65535
        stw r4, 0(r3)
        addi r3, r3, 4
        cmplwi cr0, r5, 65535
        bne cr0, LBB1_1 ;cond_next

This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.

llvm-svn: 35590
 2007-04-02 05:59:42 +00:00
Lauro Ramos Venancio
7e21418680 - Divides the comparisons in two types: comparisons that only use N and Z 
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).

llvm-svn: 35573
 2007-04-02 01:30:03 +00:00
Chris Lattner
4fb170e47b fix breakage from last night, simplify code. 
llvm-svn: 35560
 2007-04-01 20:49:36 +00:00
Evan Cheng
949a34fbad Add i16 address mode. 
llvm-svn: 35551
 2007-04-01 08:06:46 +00:00
Andrew Lenharth
ff1ff37be9 Readme 
llvm-svn: 35533
 2007-03-31 15:05:44 +00:00
Anton Korobeynikov
db09256c9f Consistency with native compilers 
llvm-svn: 35532
 2007-03-31 13:11:52 +00:00
Bill Wendling
8f16f4bf9c Fix comment. 
llvm-svn: 35531
 2007-03-31 09:36:12 +00:00
Chris Lattner
cea5e599ed add a note 
llvm-svn: 35530
 2007-03-31 07:06:25 +00:00
Bill Wendling
0cba5d3c15 Match GCC's MMX calling convention. 
llvm-svn: 35523
 2007-03-31 01:03:53 +00:00
Chris Lattner
c0405a348d implement the new addressing mode description hook. 
llvm-svn: 35521
 2007-03-30 23:15:24 +00:00
Bill Wendling
503f3e41f6 Add MMX calling conventions. 
llvm-svn: 35489
 2007-03-30 00:35:22 +00:00
Evan Cheng
526a67c09b New entry. 
llvm-svn: 35480
 2007-03-29 21:40:13 +00:00
Evan Cheng
3a6b488265 Can't re-materialize mov r, imm in thumb since mov would clobber the condition code. 
llvm-svn: 35479
 2007-03-29 21:38:31 +00:00
Jeff Cohen
67dbe2064f MS C does have inlining after all, just uses _inline instead of inline. 
llvm-svn: 35467
 2007-03-29 17:42:21 +00:00
Evan Cheng
bde0409264 Add support for hidden visibility to darwin/arm. 
llvm-svn: 35448
 2007-03-29 07:49:34 +00:00
Jeff Cohen
9193778f39 Fix C Backend to generate code that works with Microsoft C for the benefit of 
front ends that do not depend on the GCC runtime (someday...).

llvm-svn: 35441
 2007-03-28 23:08:37 +00:00
Bill Wendling
0549ae5cdb Made this into a bug report: PR1286 
llvm-svn: 35439
 2007-03-28 19:07:34 +00:00
Anton Korobeynikov
1a8740c88b Oops :) 
llvm-svn: 35438
 2007-03-28 18:38:33 +00:00
Anton Korobeynikov
d59c4e54c7 Don't allow MatchAddress recurse too much. This trims exponential 
behaviour in some cases.

llvm-svn: 35437
 2007-03-28 18:36:33 +00:00
Chris Lattner
a710f7442c add a note 
llvm-svn: 35435
 2007-03-28 18:17:19 +00:00
Chris Lattner
26a37bfd6a Compile CodeGen/X86/lea-3.ll:test2 to: 
_test3:
        leaq (,%rdi,4), %rax
        orq %rdi, %rax
        ret

instead of:
_test2:
        movq %rdi, %rax
        shlq $2, %rax
        orq %rdi, %rax
        ret

llvm-svn: 35434
 2007-03-28 18:12:31 +00:00
Chris Lattner
1f18012438 Dan pointed out that this is done, remove it! 
llvm-svn: 35430
 2007-03-28 17:26:52 +00:00
Scott Michel
ae7090641f First test check-in. 
llvm-svn: 35429
 2007-03-28 17:04:43 +00:00
Evan Cheng
a55449c051 Remove isLegalAddressImmediate. 
llvm-svn: 35406
 2007-03-28 01:53:55 +00:00
Bill Wendling
e8eccb1684 Remove cruft I put in there... 
llvm-svn: 35394
 2007-03-28 01:02:54 +00:00
Chris Lattner
9f59529c61 Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the 
system assembler not groking legal instructions like "leal (,%esi,8), %ecx".

llvm-svn: 35393
 2007-03-28 00:58:40 +00:00
Bill Wendling
1087888176 Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic. 
llvm-svn: 35392
 2007-03-28 00:57:11 +00:00
Bill Wendling
6b555c80c0 Add the "unpack low packed data" instructions. This should be the last of 
the MMX instructions that are needed...

llvm-svn: 35389
 2007-03-27 21:20:36 +00:00
Bill Wendling
d43819da2f Fix so that pandn is emitted instead of an xor/and combo. Add integer 
comparison operators.

llvm-svn: 35385
 2007-03-27 20:22:40 +00:00
Lauro Ramos Venancio
99fca527d3 "The C standards do say that "char" may either be a "signed char" or "unsigned 
char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php

llvm-svn: 35382
 2007-03-27 16:33:08 +00:00
Lauro Ramos Venancio
8b2e32de5a bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Evan Cheng
968135bd3f findRegisterUseOperand() changed. 
llvm-svn: 35366
 2007-03-26 22:41:48 +00:00
Bill Wendling
8065cc3173 Promote to v1i64 type... 
llvm-svn: 35353
 2007-03-26 08:03:33 +00:00
Bill Wendling
3c4e130b77 Updated. 
llvm-svn: 35352
 2007-03-26 07:55:58 +00:00
Bill Wendling
a42484728c Add support for the v1i64 type. This makes better code for this: 
#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

llvm-svn: 35351
 2007-03-26 07:53:08 +00:00
Anton Korobeynikov
a5e854461f Fix authorship 
llvm-svn: 35337
 2007-03-25 13:44:26 +00:00
Chris Lattner
ee90a087a6 add a note 
llvm-svn: 35334
 2007-03-25 05:10:46 +00:00
Chris Lattner
6d8bbccee0 add a note 
llvm-svn: 35330
 2007-03-25 04:46:28 +00:00
Chris Lattner
31c6763051 Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll 
llvm-svn: 35329
 2007-03-25 04:44:03 +00:00
Chris Lattner
b19069959d switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Chris Lattner
18c3c6a01d Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. 
llvm-svn: 35320
 2007-03-25 02:01:03 +00:00
Chris Lattner
104e73382c enforce the proper range for the i386 N constraint. 
llvm-svn: 35319
 2007-03-25 01:57:35 +00:00
Chris Lattner
92e2ee7b2d Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
llvm-svn: 35318
 2007-03-25 01:44:57 +00:00
Chris Lattner
a04981fbda add a bad case evan though of. 
llvm-svn: 35296
 2007-03-24 06:01:32 +00:00
Anton Korobeynikov
63bff8af0c Autodetect MMX & SSE stuff for AMD processors 
llvm-svn: 35292
 2007-03-23 23:46:48 +00:00
Bill Wendling
124f2c8706 PR1260: 
Add final support to get the QT example to compile.

llvm-svn: 35290
 2007-03-23 22:35:46 +00:00
Bill Wendling
e6a9c6dfe6 We generate a shufflevector instruction, so we don't need the builtin 
intrinsic.

llvm-svn: 35269
 2007-03-22 20:29:26 +00:00
Bill Wendling
1bcad4c1cd Support added for shifts and unpacking MMX instructions. 
llvm-svn: 35266
 2007-03-22 18:42:45 +00:00
Dale Johannesen
44c0a5d545 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Anton Korobeynikov
c0842af02d Add TODO list for MSIL backend 
llvm-svn: 35244
 2007-03-21 21:48:59 +00:00
Anton Korobeynikov
bc43d296b2 Let the new backend begin! 
llvm-svn: 35242
 2007-03-21 21:38:25 +00:00
Dale Johannesen
fb7b59f5dd add generation of unnecessary push/pop around calls 
llvm-svn: 35241
 2007-03-21 21:16:39 +00:00
Nicolas Geoffray
205541ef78 Protect R31's frame offset from being used by callee-saved registers, when R31 
is the frame pointer.

llvm-svn: 35233
 2007-03-21 16:44:14 +00:00
Evan Cheng
00a5cbf9e7 Mark re-materializable instructions. 
llvm-svn: 35230
 2007-03-21 00:16:56 +00:00
Evan Cheng
fb9c4c2edc Updated. 
llvm-svn: 35229
 2007-03-20 22:32:39 +00:00
Dale Johannesen
3e422e3b49 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Lauro Ramos Venancio
11d7d3fcaf bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Evan Cheng
4fec9d7228 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng
11976abd1e New entry. 
llvm-svn: 35206
 2007-03-20 08:10:17 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Chris Lattner
b9cc0ade43 Two changes: 
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204
 2007-03-20 06:08:29 +00:00
Chris Lattner
1ed603c0d9 fix indentation 
llvm-svn: 35202
 2007-03-20 02:25:53 +00:00
Dale Johannesen
c526b970ce fix obvious comment bug 
llvm-svn: 35196
 2007-03-20 00:30:56 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng
498f19548c Added isReMaterializable. 
llvm-svn: 35160
 2007-03-19 06:22:07 +00:00
Chris Lattner
59fe2be1c4 fix a warning 
llvm-svn: 35152
 2007-03-19 00:39:32 +00:00
Chris Lattner
a1df6908d2 minor updates 
llvm-svn: 35143
 2007-03-18 22:41:33 +00:00
Nick Lewycky
04ecc07c25 This is implemented. We now generate: 
entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

llvm-svn: 35142
 2007-03-18 14:37:20 +00:00
Devang Patel
2dabb16eac Support 'I' inline asm constraint. 
llvm-svn: 35129
 2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio
f756184c5e Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Bill Wendling
8ced23ee5a And now support for MMX logical operations. 
llvm-svn: 35125
 2007-03-16 09:44:46 +00:00
Evan Cheng
4858c6f781 Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Bill Wendling
feaff80149 Multiplication support for MMX. 
llvm-svn: 35118
 2007-03-15 21:24:36 +00:00
Evan Cheng
00edaa08b5 Under X86-64 large code model, do not emit 32-bit pc relative calls. 
llvm-svn: 35108
 2007-03-14 22:11:11 +00:00
Evan Cheng
fc80b5b712 Notes about codegen issues. 
llvm-svn: 35107
 2007-03-14 21:03:53 +00:00
Evan Cheng
50a0af3b57 Clean up. 
llvm-svn: 35105
 2007-03-14 20:20:19 +00:00
Evan Cheng
2617c8dd3a Oops. 
llvm-svn: 35104
 2007-03-14 19:44:58 +00:00
Evan Cheng
371b8e8fa9 X86-64 JIT is in large code model. Need stubs for direct calls. 
llvm-svn: 35097
 2007-03-14 10:51:55 +00:00
Evan Cheng
1092e481ce x86-64 JIT stub codegen. 
llvm-svn: 35096
 2007-03-14 10:48:08 +00:00
Evan Cheng
15de6714a4 Preliminary support for X86-64 JIT stub codegen. 
llvm-svn: 35095
 2007-03-14 10:44:30 +00:00
Evan Cheng
7cbde8351a AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] 
llvm-svn: 35088
 2007-03-13 21:05:54 +00:00
Evan Cheng
7b24b3e474 Zero is always a legal AM immediate. 
llvm-svn: 35087
 2007-03-13 20:37:59 +00:00
Nicolas Geoffray
9c77df75ea Stack and register alignment of call arguments in the ELF ABI 
llvm-svn: 35083
 2007-03-13 15:02:46 +00:00
Evan Cheng
92712d4884 Implement getTargetLowering() or else LSR won't be using ARM specific hooks. 
llvm-svn: 35077
 2007-03-13 01:20:42 +00:00
Evan Cheng
7767159f08 Updated TargetLowering LSR addressing mode hooks for ARM and Thumb. 
llvm-svn: 35075
 2007-03-12 23:30:29 +00:00
Evan Cheng
06d83c8fce More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
llvm-svn: 35074
 2007-03-12 23:29:01 +00:00
Evan Cheng
0eeb8b59eb More flexible TargetLowering LSR hooks for testing whether an immediate is 
a legal target address immediate or scale.

llvm-svn: 35073
 2007-03-12 23:28:50 +00:00
Evan Cheng
4224fa3617 Stupid bug: SSE2 supports v2i64 add / sub. 
llvm-svn: 35070
 2007-03-12 22:58:52 +00:00
Bill Wendling
236cfc4344 Adding more arithmetic operators to MMX. This is an almost exact copy of 
the addition. Please let me know if you have suggestions.

llvm-svn: 35055
 2007-03-10 09:57:05 +00:00
Evan Cheng
a4e410aa9c Minor stuff. 
llvm-svn: 35049
 2007-03-09 19:46:06 +00:00
Evan Cheng
d7201d12af Add comments about LSR / ARM. 
llvm-svn: 35048
 2007-03-09 19:35:33 +00:00
Evan Cheng
2e6f19d8c8 Unfinished work and ideas related to register scavenger. 
llvm-svn: 35047
 2007-03-09 19:34:51 +00:00
Dale Johannesen
10a05b538d apply comments from review of last patch 
llvm-svn: 35045
 2007-03-09 19:18:59 +00:00
Dale Johannesen
23c2498e23 Add some observations from CoreGraphics benchmark. Remove register 
scavenging todo item, since it is now implemented.

llvm-svn: 35044
 2007-03-09 17:58:17 +00:00
Evan Cheng
7ef8db2fb5 Implement inline asm modifier c. 
llvm-svn: 35035
 2007-03-08 22:42:46 +00:00
Bill Wendling
5fef3fd7e7 Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that 
moves, loads, etc. are recognized.

llvm-svn: 35031
 2007-03-08 22:09:11 +00:00
Evan Cheng
6445ce2423 Fix a typo. 
llvm-svn: 35030
 2007-03-08 21:59:30 +00:00
Evan Cheng
7d528d089c Putting more constants which do not contain relocations into .literal{4|8|16} 
llvm-svn: 35026
 2007-03-08 08:31:54 +00:00
Evan Cheng
393fd04eb4 Change register allocation order to Dale's suggestion. 
llvm-svn: 35021
 2007-03-08 02:56:40 +00:00
Evan Cheng
2c3e4ab3a6 Bug fix. Not advancing the register scavenger iterator correctly. 
llvm-svn: 35020
 2007-03-08 02:55:08 +00:00
Evan Cheng
c79408b032 For Darwin, put constant data into .const, .const_data, .literal{4|8|16} 
sections.

llvm-svn: 35017
 2007-03-08 01:25:25 +00:00
Evan Cheng
14b63d89c1 Put constant data to .const, .const_data, .literal{4|8|16} sections. 
llvm-svn: 35016
 2007-03-08 01:07:07 +00:00
Evan Cheng
6bf2f3665e Add ReadOnlySection directive. 
llvm-svn: 35015
 2007-03-08 01:00:38 +00:00
Evan Cheng
51c3e53eb7 Only safe to use a call-clobbered or spilled callee-saved register as scratch register. 
llvm-svn: 35010
 2007-03-07 20:30:36 +00:00
Bill Wendling
8f49ba1000 Remove useless pattern fragments. 
llvm-svn: 35009
 2007-03-07 18:23:09 +00:00
Anton Korobeynikov
85d6c1ebad Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.

llvm-svn: 35008
 2007-03-07 16:25:09 +00:00
Bill Wendling
3c201ddd02 Properly support v8i8 and v4i16 types. It now converts them to v2i32 for 
load and stores.

llvm-svn: 35002
 2007-03-07 05:43:18 +00:00
Anton Korobeynikov
090c2d50ea Fix DWARF debugging information on x86/Linux and (hopefully) 
Mingw32/Cygwin targets. This fixes PR978

llvm-svn: 35000
 2007-03-07 02:47:57 +00:00
Evan Cheng
493960579f ARM always use register scavenger. No longer reserves R12. 
llvm-svn: 34999
 2007-03-07 02:46:23 +00:00
Evan Cheng
4e01b11512 Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions. 
llvm-svn: 34998
 2007-03-07 02:38:05 +00:00
Evan Cheng
9839628fd1 Fix one more Thumb eliminateFrameIndex bug. 
llvm-svn: 34990
 2007-03-07 00:12:18 +00:00
Evan Cheng
63ffd3e17f Register scavenging is now on by default for ARM. 
llvm-svn: 34987
 2007-03-06 22:02:53 +00:00
Evan Cheng
6453ad00d2 Make load / store optimizer use register scavenger. 
llvm-svn: 34986
 2007-03-06 21:59:20 +00:00
Bill Wendling
a02d43fbbd Add LOAD/STORE support for MMX. 
llvm-svn: 34978
 2007-03-06 18:53:42 +00:00
Evan Cheng
228403bfcb Code clean up. Prepare to use register scavenger. 
llvm-svn: 34976
 2007-03-06 18:02:41 +00:00
Evan Cheng
b0c0d22f30 Minor interface change. 
llvm-svn: 34967
 2007-03-06 10:05:14 +00:00
Evan Cheng
7c90fb2d67 Scavenge a register using the register scavenger when needed. 
llvm-svn: 34966
 2007-03-06 10:03:56 +00:00
Anton Korobeynikov
6da6c8c48b Use new SDIselParamAttr enumeration. This removes "magick" constants 
from formal attributes' flags processing.

llvm-svn: 34963
 2007-03-06 08:12:33 +00:00
Chris Lattner
26a5492049 Switch PPC return lower to use an autogenerated CC description. 
llvm-svn: 34940
 2007-03-06 00:59:59 +00:00
Bill Wendling
c52174dee3 Add the emms intrinsic for MMX support. 
llvm-svn: 34938
 2007-03-05 23:09:45 +00:00
Lauro Ramos Venancio
3f855f6a54 Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS. 
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.

llvm-svn: 34931
 2007-03-05 17:59:58 +00:00
Jeff Cohen
98c99a3a02 Unbreak VC++ build. 
llvm-svn: 34917
 2007-03-05 00:00:42 +00:00
Chris Lattner
6d7701714e add missing braces 
llvm-svn: 34905
 2007-03-04 06:13:52 +00:00
Reid Spencer
e0d00951c2 Make sure that when we store a value it is masked to its correct bit 
width. This helps CBE work with non-standard integer bit widths.

llvm-svn: 34885
 2007-03-03 16:33:33 +00:00
Nick Lewycky
cfed5f36a1 Emit low/high immediate loads properly for Linux/PPC. 
llvm-svn: 34871
 2007-03-03 05:29:51 +00:00
Evan Cheng
2fb461c1b5 X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8* }. 
llvm-svn: 34857
 2007-03-02 23:16:35 +00:00
Anton Korobeynikov
7cec92bcd2 Simplify things 
llvm-svn: 34849
 2007-03-02 21:50:27 +00:00
Chris Lattner
55dcf58453 argument lowering should copy from the vreg shadows of live-in arguments 
passed in registers, not directly from the pregs themselves.

llvm-svn: 34838
 2007-03-02 05:12:29 +00:00
Chris Lattner
e29ef5d9cb add a note 
llvm-svn: 34837
 2007-03-02 05:04:52 +00:00
Dale Johannesen
a6003a9eb6 eliminate unnecessary reset of SP in epilog on darwin 
llvm-svn: 34824
 2007-03-02 01:17:17 +00:00