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Commit Graph

70561 Commits

Author SHA1 Message Date
Andrew Trick
e0442babf1 whitespace
llvm-svn: 127589
2011-03-14 16:48:10 +00:00
Justin Holewinski
a2f7c8557c PTX: Emit global arrays with proper sizes
- Emit all arrays as type .b8 and proper sizes in bytes to conform
  to the output of nvcc

llvm-svn: 127584
2011-03-14 15:40:11 +00:00
Justin Holewinski
995d10cfea PTX: Add support for sqrt/sin/cos intrinsics
llvm-svn: 127578
2011-03-14 14:09:33 +00:00
Che-Liang Chiou
6ff0aa8ab3 ptx: add set.p instruction and related changes to predicate execution
llvm-svn: 127577
2011-03-14 11:26:01 +00:00
Mikhail Glushenkov
5a7b935681 Emacs mode string.
llvm-svn: 127576
2011-03-14 04:20:57 +00:00
Francois Pichet
0e434150f9 Correct small comment order typo.
llvm-svn: 127575
2011-03-14 02:30:32 +00:00
Jin-Gu Kang
9d52ff5473 This case is solved by Scalar Replacement of Aggregates (DT) and
Early CSE pass so this patch reverts it to original source code.

llvm-svn: 127574
2011-03-14 01:21:00 +00:00
Che-Liang Chiou
962612fc5c ptx: add basic support of predicate execution
llvm-svn: 127569
2011-03-13 17:26:00 +00:00
Jin-Gu Kang
5000ba8961 Add comment as following:
load and store reference same memory location, the memory location
is represented by getelementptr with two uses (load and store) and
the getelementptr's base is alloca with single use. At this point,
instructions from alloca to store can be removed.
(this pattern is generated when bitfield is accessed.)
For example,
%u = alloca %struct.test, align 4               ; [#uses=1]
%0 = getelementptr inbounds %struct.test* %u, i32 0, i32 0;[#uses=2]
%1 = load i8* %0, align 4                       ; [#uses=1]
%2 = and i8 %1, -16                             ; [#uses=1]
%3 = or i8 %2, 5                                ; [#uses=1]
store i8 %3, i8* %0, align 4

llvm-svn: 127565
2011-03-13 14:05:51 +00:00
Oscar Fuentes
d57f14037a LTO is not ready for Windows.
llvm-svn: 127562
2011-03-13 03:06:59 +00:00
Jakob Stoklund Olesen
7d23be25ab Now that we are deleting unused live intervals during allocation, pointers may be reused.
Use the virtual register number as a cache tag instead. They are not reused.

llvm-svn: 127561
2011-03-13 01:29:32 +00:00
Jakob Stoklund Olesen
2d87d5139b Tell the register allocator about new unused virtual registers.
This allows the allocator to free any resources used by the virtual register,
including physical register assignments.

llvm-svn: 127560
2011-03-13 01:23:11 +00:00
Oscar Fuentes
e747eabef1 Build EnhancedDisassembly as a shared library too.
llvm-svn: 127555
2011-03-12 22:01:47 +00:00
Oscar Fuentes
208de1fcc4 Build CompilerDriver library.
llvm-svn: 127554
2011-03-12 22:01:42 +00:00
Oscar Fuentes
a153a45c99 Build LTO as a static library too.
llvm-svn: 127553
2011-03-12 22:01:36 +00:00
Oscar Fuentes
eef24d34e6 Build LTO as a static library too.
llvm-svn: 127549
2011-03-12 17:32:30 +00:00
Benjamin Kramer
5986a24bae Teach ComputeMaskedBits about sub nsw.
llvm-svn: 127548
2011-03-12 17:18:11 +00:00
Oscar Fuentes
443b4dd3ca Whe we build a shared library, add its list of used libraries to the
link command.

Fixed a pair of IF expressions too.

llvm-svn: 127546
2011-03-12 16:48:54 +00:00
Oscar Fuentes
471e660c5a Update link components for llvm-dis and LTO.
llvm-svn: 127545
2011-03-12 16:48:49 +00:00
Duncan Sands
0514e10276 Speculatively revert commit 127478 (jsjodin) in an attempt to fix the
llvm-gcc-i386-linux-selfhost and llvm-x86_64-linux-checks buildbots.
The original log entry:
Remove optimization emitting a reference insted of label difference, since
it can create more relocations. Removed isBaseAddressKnownZero method,
because it is no longer used.

llvm-svn: 127540
2011-03-12 13:07:37 +00:00
Jin-Gu Kang
5e537a9449 This patch removes some of useless instructions generated by bitfield access.
llvm-svn: 127539
2011-03-12 12:18:44 +00:00
Jakob Stoklund Olesen
6d02ddbbc3 Include snippets in the live stack interval.
llvm-svn: 127530
2011-03-12 04:25:36 +00:00
Jakob Stoklund Olesen
1f9f236b8a Spill multiple registers at once.
Live range splitting can create a number of small live ranges containing only a
single real use. Spill these small live ranges along with the large range they
are connected to with copies. This enables memory operand folding and maximizes
the spill to fill distance.

Work in progress with known bugs.

llvm-svn: 127529
2011-03-12 04:17:20 +00:00
Sean Callanan
4f6e58ff09 Fixed the comparison operator for the enhanced
disassembler's disassembler map.

llvm-svn: 127527
2011-03-12 03:27:54 +00:00
Jakob Stoklund Olesen
925b25d53d That's it, I am declaring this a failure of the C++03 STL.
There are too many compatibility problems with using mixed types in
std::upper_bound, and I don't want to spend 110 lines of boilerplate setting up
a call to a 10-line function. Binary search is not /that/ hard to implement
correctly.

I tried terminating the binary search with a linear search, but that actually
made the algorithm slower against my expectation. Most live intervals have less
than 4 segments. The early test against endIndex() does pay, and this version is
25% faster than plain std::upper_bound().

llvm-svn: 127522
2011-03-12 01:50:35 +00:00
Eric Christopher
392d8f7d08 Saving files before committing is overrated.
Add a RUN line to this test.

llvm-svn: 127520
2011-03-12 01:36:23 +00:00
Eric Christopher
80a45901e0 Sometimes isPredicable lies to us and tells us we don't need the operands.
Go ahead and add them on when we might want to use them and let
later passes remove them.

Fixes rdar://9118569

llvm-svn: 127518
2011-03-12 01:09:29 +00:00
Jim Grosbach
a87f223848 Remove no-longer-correct special case for disasm of ARM BL instructions.
llvm-svn: 127517
2011-03-12 01:05:29 +00:00
Jim Grosbach
f7531e7697 Add FIXME.
llvm-svn: 127516
2011-03-12 00:51:00 +00:00
Jim Grosbach
555d910477 Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the same
actual instruction as the non-Darwin defs, but have different call-clobber
semantics and so need separate patterns. They don't need to duplicate the
encoding information, however.

llvm-svn: 127515
2011-03-12 00:45:26 +00:00
Jim Grosbach
923c731f15 Add a FIXME.
llvm-svn: 127511
2011-03-11 23:25:21 +00:00
Jim Grosbach
daffeb06fb Pseudo-ize the ARM 'B' instruction.
llvm-svn: 127510
2011-03-11 23:24:15 +00:00
Jim Grosbach
2226dfbea2 Remove dead code. These ARM instruction definitions no longer exist.
llvm-svn: 127509
2011-03-11 23:15:02 +00:00
Jim Grosbach
01a937ac07 Remove dead code. These ARM instruction definitions no longer exist.
llvm-svn: 127508
2011-03-11 23:11:41 +00:00
Jim Grosbach
009af69d6d Pseudo-ize VMOVDcc and VMOVScc.
llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Jim Grosbach
61ff87cd2d 80 columns
llvm-svn: 127505
2011-03-11 23:00:16 +00:00
Jim Grosbach
27eaca3e0d Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-
effect that we get proper instruction printing using the "pop" mnemonic for it.

llvm-svn: 127502
2011-03-11 22:51:41 +00:00
Cameron Zwarich
bf5c9cd119 Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127498
2011-03-11 21:52:04 +00:00
Cameron Zwarich
39a49276db Fix the GCC test suite issue exposed by r127477, which was caused by stack
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.

llvm-svn: 127497
2011-03-11 21:51:56 +00:00
Owen Anderson
78afadfa5d Teach FastISel to support register-immediate-immediate instructions.
llvm-svn: 127496
2011-03-11 21:33:55 +00:00
Jim Grosbach
39476d9010 80 columns.
llvm-svn: 127495
2011-03-11 21:02:27 +00:00
Jim Grosbach
4ed235527d Trailing whitespace.
llvm-svn: 127493
2011-03-11 20:59:19 +00:00
Jim Grosbach
b480da2317 Remove dead code. These ARM instruction definitions don't exist.
llvm-svn: 127491
2011-03-11 20:51:07 +00:00
Jim Grosbach
ee6075cda5 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
2011-03-11 20:44:08 +00:00
Jim Grosbach
cb57d3b1d9 Remove dead code. These ARM instruction definitions don't exist.
llvm-svn: 127488
2011-03-11 20:38:18 +00:00
Jim Grosbach
3329263352 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
and VDUPLN32d, respectively.

llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
2011-03-11 20:18:05 +00:00
Jim Grosbach
fff6ff502b This FIXME has been fixed.
llvm-svn: 127483
2011-03-11 20:07:37 +00:00
Jim Grosbach
2ecded3a94 Properly pseudo-ize ARM MVNCCi.
llvm-svn: 127482
2011-03-11 19:55:55 +00:00
Jim Grosbach
9e8cf109dc Add missing 'return on failure'. Previously we'd crash after emitting
the diagnostic.

llvm-svn: 127480
2011-03-11 19:52:52 +00:00