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Commit Graph

43 Commits

Author SHA1 Message Date
Richard Osborne
b469141419 Add intrinsics for the zext / sext instructions. 
llvm-svn: 135476
 2011-07-19 13:28:50 +00:00
Richard Osborne
50303e0d38 Add intrinsics for the testct, testwct instructions. 
llvm-svn: 135475
 2011-07-19 13:00:40 +00:00
Richard Osborne
409c0d7768 Add intrinsics for the peek and endin instructions. 
llvm-svn: 135474
 2011-07-19 12:50:25 +00:00
Richard Osborne
660fe84614 Fix 80 column violations. 
llvm-svn: 132341
 2011-05-31 16:30:33 +00:00
Richard Osborne
4293c93896 Add XCore intrinsic for crc8. 
llvm-svn: 132340
 2011-05-31 16:24:49 +00:00
Richard Osborne
34a4652dcd Add XCore intrinsic for crc32. 
llvm-svn: 132336
 2011-05-31 14:47:36 +00:00
Richard Osborne
5b9df0d075 Add XCore intrinsics for initializing / starting / synchronizing threads. 
llvm-svn: 128633
 2011-03-31 15:13:13 +00:00
Richard Osborne
6bad79b514 Add XCore intrinsic for setpsc. 
llvm-svn: 127821
 2011-03-17 18:42:05 +00:00
Richard Osborne
8b90369d96 Add XCore intrinsics for setclk, setrdy. 
llvm-svn: 127761
 2011-03-16 21:56:00 +00:00
Richard Osborne
318e25c620 Add checkevent intrinsic to check if any resources owned by the current thread 
can event.

llvm-svn: 127741
 2011-03-16 18:34:00 +00:00
Richard Osborne
70204c1c29 Add XCore intrinsics for getps, setps, setsr and clrsr. 
llvm-svn: 127678
 2011-03-15 13:45:47 +00:00
Richard Osborne
a8df984a31 Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00
Richard Osborne
d9564589f6 Add XCore intrinsic for clre instruction. 
llvm-svn: 126322
 2011-02-23 18:52:05 +00:00
Richard Osborne
4a55817288 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320
 2011-02-23 18:35:59 +00:00
Richard Osborne
aaac1b01fd Add XCore intrinsic for the setv instruction. 
llvm-svn: 126315
 2011-02-23 16:46:37 +00:00
Richard Osborne
2374e9683e Fix format for setc instruction. 
llvm-svn: 126314
 2011-02-23 15:20:16 +00:00
Richard Osborne
aa39bf94b4 Add XCore intrinsic for settw instruction. 
llvm-svn: 126313
 2011-02-23 14:45:03 +00:00
Richard Osborne
bd0e21b5ca Add XCore intrinsics for various instructions on ports. 
llvm-svn: 126132
 2011-02-21 18:23:30 +00:00
Richard Osborne
112cff2533 Add intrinsic for setc instruction on the XCore. 
llvm-svn: 125186
 2011-02-09 13:22:12 +00:00
Richard Osborne
5c655f451e Add XCore intrinsics for resource instructions. 
llvm-svn: 124794
 2011-02-03 13:14:25 +00:00
Chris Lattner
01e8c46349 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Jakob Stoklund Olesen
216f6cc9ae Remove Predicate_* calls from MBlaze and XCore 
llvm-svn: 112920
 2010-09-03 00:35:16 +00:00
Eric Christopher
2dae43dbe4 Remove isTwoAddress from XCore. 
llvm-svn: 106446
 2010-06-21 18:51:38 +00:00
Chris Lattner
4de7f7e862 fix a type contradition: XCoreISD::RETSP has one argument, not zero. 
llvm-svn: 99760
 2010-03-28 08:47:39 +00:00
Chris Lattner
896b393fab set SDNPVariadic on nodes throughout the rest of the targets that 
need them.

llvm-svn: 98937
 2010-03-19 05:33:51 +00:00
Richard Osborne
92fb0be76b Don't mark call instruction as a barrier. 
llvm-svn: 96983
 2010-02-23 21:08:11 +00:00
Richard Osborne
eb0446c12a ECALLF, ECALLT shouldn't be marked as barriers. 
llvm-svn: 96964
 2010-02-23 18:29:49 +00:00
Richard Osborne
9abd3b3ca7 Mark unconditional branches as barriers. Found using -verify-machineinstrs 
llvm-svn: 96960
 2010-02-23 18:13:38 +00:00
Richard Osborne
7387249531 Lower BR_JT on the XCore to a jump into a series of jump instructions. 
llvm-svn: 96942
 2010-02-23 13:25:07 +00:00
Dan Gohman
92b6122204 Fix "the the" and similar typos. 
llvm-svn: 95781
 2010-02-10 16:03:48 +00:00
Richard Osborne
fc2d5141a4 Add XCore support for indirectbr / blockaddress. 
llvm-svn: 89273
 2009-11-18 23:20:42 +00:00
Dan Gohman
4631d78a3b Set isBarrier = 1 on return instructions, as they are control barriers. 
llvm-svn: 86851
 2009-11-11 18:11:07 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Richard Osborne
1719935e3f Add some peepholes for signed comparisons using ashr X, X, 32. 
llvm-svn: 83549
 2009-10-08 15:38:17 +00:00
Richard Osborne
90a7ea5c13 Remove xs1b predicate since it is no longer needed to differentiate betweem 
xs1a and xs1b.

llvm-svn: 83383
 2009-10-06 16:17:57 +00:00
Richard Osborne
b692ade672 Remove xs1a subtarget. xs1a is a preproduction device used in 
early development boards which is no longer supported in the
XMOS toolchain.

llvm-svn: 83381
 2009-10-06 16:01:09 +00:00
Richard Osborne
179bf3bdc2 Add extra SEXT pattern. 
llvm-svn: 77920
 2009-08-02 22:45:24 +00:00
Richard Osborne
bdd120fbdb Fix pattern for LD16S_3r, add basic tests to check load / store instructions 
are being properly selected.

llvm-svn: 75797
 2009-07-15 17:06:59 +00:00
Bill Wendling
8235a05c1a Untabification. 
llvm-svn: 72604
 2009-05-30 01:09:53 +00:00
Richard Osborne
12b88f2fae Add pseudo instructions to the XCore for (load|store|load address) of a 
frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.

This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.

llvm-svn: 62238
 2009-01-14 18:26:46 +00:00
Richard Osborne
e74ae9dbb7 Add support for ISD::TRAP to the XCore backend 
llvm-svn: 60479
 2008-12-03 10:59:16 +00:00
Richard Osborne
8f86bb4d20 Add XCore intrinsics for getid (returns thread id) and bitrev (reverses 
bits in a word).

llvm-svn: 59296
 2008-11-14 10:12:16 +00:00
Richard Osborne
acc7a27e24 Add XCore backend. 
llvm-svn: 58838
 2008-11-07 10:59:00 +00:00