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Commit Graph

4050 Commits

Author SHA1 Message Date
Colin LeMahieu
e11e421bc5 [Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores.
llvm-svn: 225009
2014-12-30 22:28:31 +00:00
Zoran Jovanovic
a9daa0cdb9 [mips][microMIPS] Relocate with symbol for micromips symbols
Differential Revision: http://reviews.llvm.org/D6796

llvm-svn: 225008
2014-12-30 22:04:16 +00:00
Colin LeMahieu
a76ddd9ae4 [Hexagon] Adding indexed store new-value variants.
llvm-svn: 225007
2014-12-30 22:00:26 +00:00
Colin LeMahieu
ef54aa0778 [Hexagon] Adding indexed store of immediates.
llvm-svn: 225006
2014-12-30 21:01:38 +00:00
Colin LeMahieu
4a47613bb1 [Hexagon] Adding indexed stores.
llvm-svn: 225005
2014-12-30 20:42:23 +00:00
Michael Kuperstein
a000cb8396 [COFF] Don't try to add quotes to already quoted linker directives
If a linker directive is already quoted, don't try to quote it again, otherwise it creates a mess.
This pops up in places like:
#pragma comment(linker,"\"/foo bar'\"")

Differential Revision: http://reviews.llvm.org/D6792

llvm-svn: 224998
2014-12-30 19:23:48 +00:00
Colin LeMahieu
be9ae58d93 [Hexagon] Adding reg-reg indexed load forms.
llvm-svn: 224997
2014-12-30 18:58:47 +00:00
Colin LeMahieu
c9924ffc90 [Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form.
llvm-svn: 224991
2014-12-30 17:39:24 +00:00
Colin LeMahieu
300c89d245 [Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.
llvm-svn: 224989
2014-12-30 15:44:17 +00:00
Rafael Espindola
1db8d30b1f Remove doesSectionRequireSymbols.
In an assembly expression like

bar:
.long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

llvm-svn: 224985
2014-12-30 13:13:27 +00:00
Rafael Espindola
288a7d5deb Simplify test a bit.
It looks like the original intent was to check which symbols were created.
With macho-dump the sections were being checked just to match which symbol
was in which section.

llvm-objdump prints the section a symbol is in.

llvm-svn: 224980
2014-12-30 05:09:17 +00:00
Craig Topper
fdffa281dd Testcases for r224939.
llvm-svn: 224976
2014-12-30 02:35:56 +00:00
Rafael Espindola
5370c8b346 Convert test to llvm-readobj. NFC.
llvm-svn: 224973
2014-12-30 01:34:06 +00:00
Rafael Espindola
3ba2645971 Convert test to llvm-readobj. NFC.
llvm-svn: 224959
2014-12-29 22:14:35 +00:00
Colin LeMahieu
51cfbc91d9 [Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores.
llvm-svn: 224957
2014-12-29 21:33:45 +00:00
Colin LeMahieu
d8726fd59b [Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.
llvm-svn: 224952
2014-12-29 20:44:51 +00:00
Colin LeMahieu
d92e961fd1 [Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits.
llvm-svn: 224951
2014-12-29 20:00:43 +00:00
Rafael Espindola
4e9711a8ac Convert test to FileCheck. NFC.
llvm-svn: 224950
2014-12-29 19:50:32 +00:00
Colin LeMahieu
bb631541eb [Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs.
llvm-svn: 224949
2014-12-29 19:42:14 +00:00
Rafael Espindola
202ce88279 Convert test to llvm-readobj. NFC.
llvm-svn: 224872
2014-12-26 22:47:39 +00:00
Colin LeMahieu
3c20022db5 [Hexagon] Adding auto-incrementing loads with and without byte reversal.
llvm-svn: 224871
2014-12-26 21:09:25 +00:00
Colin LeMahieu
9363870e8a [Hexagon] Adding locked loads.
llvm-svn: 224870
2014-12-26 20:42:27 +00:00
Colin LeMahieu
286196b24f [Hexagon] Adding deallocframe and circular addressing loads.
llvm-svn: 224869
2014-12-26 20:30:58 +00:00
Colin LeMahieu
80ca4bde69 [Hexagon] Adding remaining post-increment instruction variants. Removing unused classes.
llvm-svn: 224868
2014-12-26 19:31:46 +00:00
Colin LeMahieu
510942bba6 [Hexagon] Adding post-increment unsigned byte loads.
llvm-svn: 224867
2014-12-26 19:12:11 +00:00
Colin LeMahieu
e0aad91d5f [Hexagon] Adding post-increment signed byte loads with tests.
llvm-svn: 224866
2014-12-26 18:57:13 +00:00
Rafael Espindola
3fc4781cae Use llvm-readobj. NFC.
llvm-svn: 224864
2014-12-26 18:22:05 +00:00
Craig Topper
98caef7939 [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them.
llvm-svn: 224862
2014-12-26 18:20:05 +00:00
Craig Topper
955459673e [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references.
llvm-svn: 224861
2014-12-26 18:19:44 +00:00
Craig Topper
1568430176 Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4.
llvm-svn: 224846
2014-12-26 06:36:28 +00:00
David Majnemer
91e6049dc1 MC: Label definitions are permitted after .set directives
.set directives may be overridden by other .set directives as well as
label definitions.

This fixes PR22019.

llvm-svn: 224811
2014-12-24 10:27:50 +00:00
David Majnemer
0cde9facf3 MC: Don't emit .no_dead_strip on targets which don't support it
llvm-svn: 224808
2014-12-24 04:11:42 +00:00
Colin LeMahieu
3a9d8a20be [Hexagon] Adding doubleword load.
llvm-svn: 224787
2014-12-23 20:44:59 +00:00
Colin LeMahieu
c8d82f0149 [Hexagon] Reapplying 224775 load words.
llvm-svn: 224786
2014-12-23 20:02:16 +00:00
Jozef Kolek
a7fba787ce [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions
Differential Revision: http://reviews.llvm.org/D5204

llvm-svn: 224785
2014-12-23 19:55:34 +00:00
Colin LeMahieu
240787f100 Reverting 224775 until mayLoad flag is addressed.
llvm-svn: 224783
2014-12-23 19:22:59 +00:00
Colin LeMahieu
9d1882c36f [Hexagon] Adding word loads.
llvm-svn: 224775
2014-12-23 18:06:56 +00:00
Colin LeMahieu
263816de1a [Hexagon] Adding signed halfword loads.
llvm-svn: 224774
2014-12-23 17:25:57 +00:00
Jozef Kolek
814723a8ed [mips][microMIPS] Implement LWSP and SWSP instructions
Differential Revision: http://reviews.llvm.org/D6416

llvm-svn: 224771
2014-12-23 16:16:33 +00:00
Elena Demikhovsky
cfbcf5995c AVX-512: BLENDM - fixed encoding of the broadcast version
Added more intrinsics and encoding tests.

llvm-svn: 224760
2014-12-23 09:36:28 +00:00
Reid Kleckner
eecdfef0b6 Fix Windows unwind info for functions in sections other than .text
Previously we assumed the section name had the form .text$foo, which is
what we used to do for inline functions. If the dollar wasn't present,
we'd put unwind data in the .pdata and .xdata sections for the main
.text section, which is incorrect.

Fixes PR22001.

llvm-svn: 224738
2014-12-22 22:10:08 +00:00
Colin LeMahieu
b1f14d473d [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.
llvm-svn: 224735
2014-12-22 21:40:43 +00:00
Colin LeMahieu
c88fff49c9 [Hexagon] Adding classes and load unsigned byte instruction, updating usages.
llvm-svn: 224730
2014-12-22 21:20:03 +00:00
Elena Demikhovsky
aeb7ff5f14 AVX-512: Added all forms of BLENDM instructions,
intrinsics, encoding tests for AVX-512F and skx instructions.

llvm-svn: 224707
2014-12-22 13:52:48 +00:00
Saleem Abdulrasool
5b457858a7 ARM: further improve deprecated diagnosis (LDM)
The ARM ARM states:
  LDM/LDMIA/LDMFD:
    The SP can be in the list. However, ARM deprecates using these instructions
    with SP in the list.

    ARM deprecates using these instructions with both the LR and the PC in the
    list.

  LDMDA/LDMFA/LDMDB/LDMEA/LDMIB/LDMED:
    The SP can be in the list. However, instructions that include the SP in the
    list are deprecated.

    Instructions that include both the LR and the PC in the list are deprecated.

  POP:
    The SP can only be in the list before ARMv7. ARM deprecates any use of ARM
    instructions that include the SP, and the value of the SP after such an
    instruction is UNKNOWN.

    ARM deprecates the use of this instruction with both the LR and the PC in
    the list.

Attempt to diagnose use of deprecated forms of these instructions.  This mirrors
the previous changes to diagnose use of the deprecated forms of STM in ARM mode.

llvm-svn: 224682
2014-12-20 20:25:36 +00:00
Colin LeMahieu
4c325f2cef [Hexagon] Removing old variants of instructions and updating references.
llvm-svn: 224612
2014-12-19 20:29:29 +00:00
Colin LeMahieu
b1509fe128 [Hexagon] Adding bit extraction and table indexing instructions.
llvm-svn: 224610
2014-12-19 20:01:08 +00:00
Colin LeMahieu
7e0cce8462 [Hexagon] Adding bit insertion instructions.
llvm-svn: 224609
2014-12-19 19:54:38 +00:00
Colin LeMahieu
11b6034e2b [Hexagon] Adding more xtype shift instructions.
llvm-svn: 224608
2014-12-19 19:51:35 +00:00
Colin LeMahieu
b6c1e97753 [Hexagon] Adding xtype shift instructions.
llvm-svn: 224604
2014-12-19 19:34:50 +00:00