Evan Cheng
bc84a42d7b
Revert 93158. It's breaking quite a few x86_64 tests.
...
llvm-svn: 93185
2010-01-11 21:13:41 +00:00
Evan Cheng
4548543b0b
Do not turn 8-bit OR to ADD since ADD8ri is not 3-addressfiable.
...
llvm-svn: 93182
2010-01-11 20:18:04 +00:00
Benjamin Kramer
cdbc36f961
Reimplement getToken and SplitString as "StringRef helper functions"
...
- getToken is modeled after StringRef::split but it can split on multiple
separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
same behaviour as getToken.
llvm-svn: 93161
2010-01-11 18:03:24 +00:00
Dan Gohman
541c4f4c5d
Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
...
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.
FileCheckize, tidy, and extend a testcase to cover this case.
This fixes rdar://7527390.
llvm-svn: 93160
2010-01-11 17:58:34 +00:00
Dan Gohman
5b79391087
Re-instate MOV64r0 and MOV16r0, with adjustments to work with the
...
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.
llvm-svn: 93158
2010-01-11 17:37:57 +00:00
Dan Gohman
a83443605d
Pattern top-level operators don't need to be restricted to a
...
single user. The _su forms are intended for non-top-level nodes.
llvm-svn: 93155
2010-01-11 17:21:05 +00:00
Dan Gohman
5042879ae5
Reword this comment to reference a more fundamental issue.
...
llvm-svn: 93154
2010-01-11 17:14:46 +00:00
Evan Cheng
ee806a0db5
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.
...
llvm-svn: 93152
2010-01-11 17:03:47 +00:00
David Greene
b879ff4855
Implement a feature (-vector-unaligned-mem) to allow targets to
...
ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
2010-01-11 16:29:42 +00:00
Jeffrey Yasskin
53a8f3981c
Fix http://llvm.org/PR5729 : x86-64 tail calls were putting their targets into
...
R11, and then asserting that the target was in R9. Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.
llvm-svn: 93065
2010-01-09 18:56:43 +00:00
Evan Cheng
2e497d1ed4
Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock.
...
llvm-svn: 93028
2010-01-08 23:41:50 +00:00
Evan Cheng
8b248e5016
Fix comment.
...
llvm-svn: 93020
2010-01-08 19:14:57 +00:00
Eric Christopher
067afe673c
After further thought revert the patch to make fast-isel avoid
...
putting relocations into the constant pool - this isn't needed
for correctness and in the rare occasion it happens would pull
us out of fast isel for the block.
If fast-isel application startup time ever becomes an issue we
can add better support for these addresses instead of bailing.
llvm-svn: 92995
2010-01-08 08:24:49 +00:00
Evan Cheng
4f25f87baa
Fix what looks to me obvious instruction definition bugs.
...
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.
llvm-svn: 92985
2010-01-08 01:29:19 +00:00
Eric Christopher
2a3196c2e5
Remove extraneous include.
...
llvm-svn: 92972
2010-01-08 00:05:33 +00:00
Eric Christopher
d218bc7a2f
If the data requires a relocation then don't attempt to
...
add it to the constant pool for fast-isel. We already
don't add it for the normal case.
llvm-svn: 92934
2010-01-07 19:45:14 +00:00
Evan Cheng
51d86260ff
Fix a minor regression from my dag combiner changes. One more place which needs to look pass truncates.
...
llvm-svn: 92885
2010-01-07 00:54:06 +00:00
Evan Cheng
25dcf9b830
Teach dag combine to fold the following transformation more aggressively:
...
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))
Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
llvm-svn: 92849
2010-01-06 19:38:29 +00:00
Benjamin Kramer
0ba7479f2c
Move remaining stuff to the isInteger predicate.
...
llvm-svn: 92771
2010-01-05 21:05:54 +00:00
Benjamin Kramer
c233521d45
Convert a ton of simple integer type equality tests to the new predicate.
...
llvm-svn: 92760
2010-01-05 20:07:06 +00:00
Evan Cheng
3c99a6f8c3
Code refactoring.
...
llvm-svn: 92694
2010-01-05 06:52:31 +00:00
David Greene
d1475983db
Change errs() to dbgs().
...
llvm-svn: 92654
2010-01-05 01:29:34 +00:00
David Greene
05203dccf1
Change errs() to dbgs().
...
llvm-svn: 92653
2010-01-05 01:29:29 +00:00
David Greene
b5d95aa80e
Change errs() to dbgs().
...
llvm-svn: 92651
2010-01-05 01:29:23 +00:00
David Greene
8a947405d5
Change errs() to dbgs().
...
llvm-svn: 92648
2010-01-05 01:29:13 +00:00
David Greene
8a6a52d2b8
Change errs() to dbgs().
...
llvm-svn: 92647
2010-01-05 01:29:08 +00:00
David Greene
13baf4f08a
Change errs() to dbgs().
...
llvm-svn: 92644
2010-01-05 01:28:53 +00:00
Dan Gohman
9bcfdf98f1
Change SelectCode's argument from SDValue to SDNode *, to make it more
...
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
2010-01-05 01:24:18 +00:00
Dan Gohman
d3383baab0
Remove the SDNPAssociative properties for the flags-producing
...
operators. Eli pointed out that it's not obvious what that
would mean.
llvm-svn: 92555
2010-01-05 00:44:20 +00:00
Evan Cheng
275a43dadb
Perform this folding as a target specific dag combine:
...
(or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
The isel patterns may not catch all the cases if general dag combine has reduced width of source operands.
llvm-svn: 92513
2010-01-04 21:22:48 +00:00
Dan Gohman
f5f090c2c5
Remove some README.txt entries which are now implemented.
...
llvm-svn: 92511
2010-01-04 20:55:05 +00:00
Dan Gohman
5f107150ed
A use by operand 1 or 2 of a SELECT is not a FLAGS use. This
...
lets the test-elimination work in more conditional-move cases.
llvm-svn: 92508
2010-01-04 20:52:50 +00:00
Dan Gohman
f87ad693cf
Flags-producing add, and, or, etc. have the same profibility
...
rules as normal add, and, or, etc.
llvm-svn: 92507
2010-01-04 20:51:50 +00:00
Dan Gohman
29583f656d
Add SDNPCommutative and SDNPAssociative to several X86 target nodes.
...
This lets isel fold loads into them in more cases.
llvm-svn: 92506
2010-01-04 20:51:05 +00:00
Benjamin Kramer
1d24aae2db
Replace a few more SmallVectors with arrays.
...
llvm-svn: 92265
2009-12-29 16:57:26 +00:00
Bill Wendling
b96be04b8a
Remove dead variable.
...
llvm-svn: 92184
2009-12-28 01:36:02 +00:00
Eli Friedman
3a53d1cb1a
PR5886: Make sure IMUL32m is marked as setting EFLAGS, so scheduling doesn't
...
do illegal stuff around it. No testcase because the issue is very fragile.
llvm-svn: 92167
2009-12-26 20:08:30 +00:00
Chris Lattner
f77ca5f9f5
really remove the instruction, don't just comment it out
...
llvm-svn: 91976
2009-12-23 01:46:40 +00:00
Chris Lattner
d7e8bd73fe
completely eliminate the MOV16r0 'instruction'. The only
...
interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.
llvm-svn: 91975
2009-12-23 01:45:04 +00:00
Sean Callanan
0c1d56a0c8
More fixes for Visual C++. Replaced several very small
...
static inline functions with macros.
llvm-svn: 91973
2009-12-23 01:32:29 +00:00
Chris Lattner
dbcf2725aa
stop pattern matching 16-bit zero's of a register to MOV16r0,
...
instead use the appropriate subreggy thing. This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july). This means that MOV16r0 can go away
completely in the future soon.
llvm-svn: 91972
2009-12-23 01:30:26 +00:00
Sean Callanan
3ccfaafab6
Removed the "inline" keyword from the disassembler decoder,
...
because the Visual C++ build does not build .c files as C99
llvm-svn: 91935
2009-12-22 22:51:40 +00:00
Sean Callanan
983f906451
Fixes to the X86 disassembler:
...
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.
llvm-svn: 91919
2009-12-22 21:12:55 +00:00
Evan Cheng
7cd6bfe549
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
...
llvm-svn: 91910
2009-12-22 17:47:23 +00:00
Douglas Gregor
0590ad1884
Include based on the current path, since we already -I the X86 target's path. Fixes CMake build
...
llvm-svn: 91908
2009-12-22 17:25:11 +00:00
Bill Wendling
fc4c238bd5
Add more plumbing. This time in the LowerArguments and "get" functions which
...
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
llvm-svn: 91880
2009-12-22 02:10:19 +00:00
Sean Callanan
09b2d80d2c
Changed REG_* to MODRM_REG_* to avoid conflicts
...
with symbols in AuroraUX's global namespace.
llvm-svn: 91879
2009-12-22 02:07:42 +00:00
Daniel Dunbar
abb0af5166
Fix some may-be-uninitialized var warnings.
...
llvm-svn: 91878
2009-12-22 01:41:37 +00:00
Sean Callanan
feddcdf843
Fixed library dependencies between the X86 disassembler and
...
X86 codegen that were causing circular symbol dependencies.
llvm-svn: 91871
2009-12-22 01:11:26 +00:00
Chris Lattner
0651fc828b
print pcrel immediates as signed values instead of unsigned so that we
...
get things like this out of the disassembler:
0x100000ecb: callq -96
instead of:
0x100000ecb: callq 4294967200
rdar://7491123
llvm-svn: 91864
2009-12-22 00:44:05 +00:00
Eric Christopher
5c812e2396
Fix setting and default setting of code model for jit. Do this
...
by allowing backends to override routines that will default
the JIT and Static code generation to an appropriate code model
for the architecture.
Should fix PR 5773.
llvm-svn: 91824
2009-12-21 08:15:29 +00:00
Eli Friedman
50c8e9154f
A couple minor README updates.
...
llvm-svn: 91823
2009-12-21 08:03:16 +00:00
Daniel Dunbar
758730a9e9
#if 0 out X86 disassembler for now, it is breaking the build in multiple places.
...
llvm-svn: 91778
2009-12-19 17:11:53 +00:00
Nuno Lopes
78f040fa26
rename dprintf to dbgpritnf, in order to fix build with glibc (which already defines dprintf in stdio.h
...
llvm-svn: 91775
2009-12-19 12:07:00 +00:00
Daniel Dunbar
057ae7e82e
Use memset instead of bzero, its more portable.
...
llvm-svn: 91754
2009-12-19 03:31:50 +00:00
Sean Callanan
18fa59f381
Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit
...
incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
llvm-svn: 91749
2009-12-19 02:59:52 +00:00
Anton Korobeynikov
4e05e61a52
Bump alignment requirements for windows targets to achieve compartibility with vcpp.
...
Based on patch by Michael Beck!
llvm-svn: 91745
2009-12-19 02:04:23 +00:00
Evan Cheng
d97d025eba
On recent Intel u-arch's, folding loads into some unary SSE instructions can
...
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
llvm-svn: 91672
2009-12-18 07:40:29 +00:00
Evan Cheng
a647318eb3
Re-apply 91623 now that I actually know what I was trying to do.
...
llvm-svn: 91655
2009-12-18 01:59:21 +00:00
Sean Callanan
06b6feb2e1
Instruction fixes, added instructions, and AsmString changes in the
...
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
llvm-svn: 91638
2009-12-18 00:01:26 +00:00
Jeffrey Yasskin
f39a138a7c
Revert r91623 to unbreak the buildbots.
...
llvm-svn: 91632
2009-12-17 22:44:34 +00:00
Evan Cheng
d765952b17
Remove an unused option.
...
llvm-svn: 91623
2009-12-17 21:23:58 +00:00
Ken Dyck
319b2ed194
In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of
...
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.
llvm-svn: 91602
2009-12-17 15:31:52 +00:00
Evan Cheng
aaf2f58a04
Re-enable 91381 with fixes.
...
llvm-svn: 91489
2009-12-16 00:53:11 +00:00
Jeffrey Yasskin
d50951dc1e
Change indirect-globals to use a dedicated allocIndirectGV. This lets us
...
remove start/finishGVStub and the BufferState helper class from the
MachineCodeEmitter interface. It has the side-effect of not setting the
indirect global writable and then executable on ARM, but that shouldn't be
necessary.
llvm-svn: 91464
2009-12-15 22:42:46 +00:00
Evan Cheng
32946d6aae
Fix an encoding bug.
...
llvm-svn: 91417
2009-12-15 06:49:02 +00:00
Kenneth Uildriks
c0ab5a6e88
For fastcc on x86, let ECX be used as a return register after EAX and EDX
...
llvm-svn: 91410
2009-12-15 03:27:52 +00:00
Evan Cheng
4adb4acc7b
Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp.
...
llvm-svn: 91405
2009-12-15 03:07:11 +00:00
Evan Cheng
cd8f0de016
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
...
llvm-svn: 91381
2009-12-15 00:53:42 +00:00
Dan Gohman
57dc006590
Fix integer cast code to handle vector types.
...
llvm-svn: 91362
2009-12-14 23:40:38 +00:00
Bill Wendling
e4328758f9
Whitespace changes, comment clarification. No functional changes.
...
llvm-svn: 91274
2009-12-14 06:51:19 +00:00
Evan Cheng
ee5b5917fd
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit.
...
llvm-svn: 91223
2009-12-12 20:03:14 +00:00
Evan Cheng
5cd8cd2a5c
Add comment about potential partial register stall.
...
llvm-svn: 91220
2009-12-12 18:55:26 +00:00
Evan Cheng
53e863f152
Fix an obvious bug. No test case since LEA16r is not being used.
...
llvm-svn: 91219
2009-12-12 18:51:56 +00:00
Dan Gohman
2e616e859b
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
...
llvm-svn: 91158
2009-12-11 21:31:27 +00:00
Anton Korobeynikov
f8b2e2868e
Honour setHasCalls() set from isel.
...
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723
llvm-svn: 91144
2009-12-11 19:39:55 +00:00
Evan Cheng
01a56041a5
Add support to 3-addressify 16-bit instructions.
...
llvm-svn: 91104
2009-12-11 06:01:48 +00:00
Evan Cheng
9e2442c0be
Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.
...
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>
iff ptr is 16-byte aligned (or can be made into 16-byte aligned).
llvm-svn: 90984
2009-12-09 21:00:30 +00:00
Evan Cheng
41c13e41fe
Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
...
llvm-svn: 90925
2009-12-09 01:53:58 +00:00
Evan Cheng
7941695285
Move isConsecutiveLoad to SelectionDAG. It's not target dependent and it's primary used by selectdag passes.
...
llvm-svn: 90922
2009-12-09 01:36:00 +00:00
Dan Gohman
44e25ed254
Don't enable the post-RA scheduler on x86 except at -O3. In its
...
current form, it is too expensive in compile time.
llvm-svn: 90781
2009-12-07 19:04:31 +00:00
Dan Gohman
f9654e9258
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
...
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
llvm-svn: 90634
2009-12-05 00:44:40 +00:00
David Greene
755852d0c3
Remove an unneeded include.
...
llvm-svn: 90625
2009-12-04 23:55:07 +00:00
David Greene
cb0611ec3b
Have hasLoad/StoreFrom/ToStackSlot return the relevant MachineMemOperand.
...
llvm-svn: 90608
2009-12-04 22:38:46 +00:00
Chris Lattner
29e2e60be6
yay for case insensitive file systems (?)
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llvm-svn: 90370
2009-12-03 01:10:05 +00:00
Chris Lattner
9ce833945e
improve portability to avoid conflicting with std::next in c++'0x.
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Patch by Howard Hinnant!
llvm-svn: 90365
2009-12-03 00:50:42 +00:00
Jim Grosbach
0e1230b23b
Factor the stack alignment calculations out into a target independent pass.
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No functionality change.
llvm-svn: 90336
2009-12-02 19:30:24 +00:00
Dan Gohman
e573c59c90
Minor whitespace fixes.
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llvm-svn: 90166
2009-11-30 23:33:53 +00:00
Dan Gohman
af05157fde
Fix a minor inconsistency.
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llvm-svn: 90165
2009-11-30 23:33:37 +00:00
Bob Wilson
b293fe32cb
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
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for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
llvm-svn: 90144
2009-11-30 18:35:03 +00:00
Mon P Wang
27bce4e285
Added support to allow clients to custom widen. For X86, custom widen vectors for
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divide/remainder since these operations can trap by unroll them and adding undefs
for the resulting vector.
llvm-svn: 90108
2009-11-30 02:42:02 +00:00
Bob Wilson
aee7a9e676
Based on the testcase for pr3120, running on my MacPro with Xeon processors,
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it is definitely profitable to tail duplicate indirect branches for x86.
This is likely to be true to various degrees for all modern x86 processors.
llvm-svn: 89865
2009-11-25 17:27:53 +00:00
Daniel Dunbar
ffe6484b7c
Sketch structure for X86 disassembler.
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llvm-svn: 89850
2009-11-25 06:53:08 +00:00
Jeffrey Yasskin
0a0b21f8c5
* Move stub allocation inside the JITEmitter, instead of exposing a
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way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816 .
* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.
llvm-svn: 89715
2009-11-23 23:35:19 +00:00
Dan Gohman
b5ec39e2dc
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
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Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
Jeffrey Yasskin
ed6d1ce9ae
Allow more than one stub to be being generated at the same time.
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It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.
llvm-svn: 89708
2009-11-23 22:49:00 +00:00
Devang Patel
327919890c
We are not using DBG_STOPPOINT anymore.
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llvm-svn: 89536
2009-11-21 02:46:55 +00:00
Dan Gohman
e5eddcd606
Fix a thinko that caused spurious @GOTOFFs.
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llvm-svn: 89509
2009-11-20 23:30:32 +00:00
Dan Gohman
3517f425b8
Target-independent support for TargetFlags on BlockAddress operands,
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and support for blockaddresses in x86-32 PIC mode.
llvm-svn: 89506
2009-11-20 23:18:13 +00:00
Sean Callanan
78ee7f5d57
Recommitting PALIGNR shift width fixes.
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Thanks to Daniel Dunbar for fixing clang intrinsics:
http://llvm.org/viewvc/llvm-project?view=rev&revision=89499
llvm-svn: 89500
2009-11-20 22:28:42 +00:00