Anton Korobeynikov
f7651ec593
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
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Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).
Allow unaligned memops on darwin and conservatively disallow them otherwise.
llvm-svn: 94889
2010-01-30 14:08:12 +00:00
Chris Lattner
ee2b6b1cc5
emit jump table an alias ".set" directives through MCStreamer as
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assignments.
.set x, a-b
is the same as:
x = a-b
llvm-svn: 94596
2010-01-26 21:53:08 +00:00
Rafael Espindola
f46baf3304
Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF.
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Original patch by Sandeep Patel and updated by me.
llvm-svn: 94582
2010-01-26 20:21:43 +00:00
Rafael Espindola
575697fd65
Update test for darwin.
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llvm-svn: 94421
2010-01-25 15:32:10 +00:00
Rafael Espindola
82a8b3efd4
Fix PR6134.
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We are not emitting alignments on Darwin for "bar". Not sure what is the
correct way to do it.
llvm-svn: 94400
2010-01-25 02:27:39 +00:00
Dan Gohman
525f7d7833
Revert LoopStrengthReduce.cpp to pre-r94061 for now.
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llvm-svn: 94123
2010-01-22 00:46:49 +00:00
Dan Gohman
be34c35f32
Re-implement the main strength-reduction portion of LoopStrengthReduction.
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This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.
It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.
llvm-svn: 94061
2010-01-21 02:09:26 +00:00
Evan Cheng
572390be3b
Test case for r93758.
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llvm-svn: 93824
2010-01-19 00:35:20 +00:00
Bob Wilson
72cf548263
The Neon "vtst" instruction takes a suffix that is the element size alone --
...
adding an "i" to the suffix, indicating that the elements are integers, is
accepted but not part of the standard syntax. This helps us pass a few more
of the Neon tests from gcc.
llvm-svn: 93677
2010-01-17 06:35:17 +00:00
Bob Wilson
3386047bdb
Run the pre-register allocation tail duplication pass by default. Remove
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the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.
llvm-svn: 93597
2010-01-16 00:29:50 +00:00
Chris Lattner
1b6c061cd0
remove uses of deprecated functions, this generates slightly
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different BlockAddress labels, but nothing semantically important.
Add a FIXME that BlockAddress codegen is broken if the LLVM BB has
an empty name (e.g. strip was run).
llvm-svn: 93303
2010-01-13 07:30:49 +00:00
Dan Gohman
5fa04f2707
Delete useless trailing semicolons.
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llvm-svn: 92740
2010-01-05 17:55:26 +00:00
Chris Lattner
3d38dbff2a
Make this more likely to generate a libcall.
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llvm-svn: 92387
2010-01-01 03:26:51 +00:00
Bob Wilson
a9f20f9f6e
Handle ARM inline asm "w" constraints with 64-bit ("d") registers.
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The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
llvm-svn: 91649
2009-12-18 01:03:29 +00:00
Evan Cheng
edcc21919f
- Support inline asm 'w' constraint for 128-bit vector types.
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- Also support the 'q' NEON registers asm code.
llvm-svn: 90894
2009-12-08 23:06:22 +00:00
Bob Wilson
b53c801366
Recognize canonical forms of vector shuffles where the same vector is used for
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both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
llvm-svn: 90417
2009-12-03 06:40:55 +00:00
Evan Cheng
fcbc30f36e
Fix PR5614: parts of a physical register def may be killed the rest.
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llvm-svn: 90180
2009-12-01 00:44:45 +00:00
Anton Korobeynikov
0f885eb7fd
Materialize global addresses via movt/movw pair, this is always better
...
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
llvm-svn: 89720
2009-11-24 00:44:37 +00:00
Jim Grosbach
76b545e988
move fconst[sd] to UAL. <rdar://7414913>
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llvm-svn: 89700
2009-11-23 21:08:25 +00:00
Edward O'Callaghan
d1c7b40bb5
Convert ARM tests to FileCheck for PR5307.
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llvm-svn: 89593
2009-11-22 14:23:33 +00:00
Edward O'Callaghan
1a250b4109
Forgot to alter RUN line when converting to FileCheck.
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llvm-svn: 89588
2009-11-22 13:09:48 +00:00
Edward O'Callaghan
5ae4559914
Fix for bad FileCheck converts in revision 89584.
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llvm-svn: 89586
2009-11-22 12:50:05 +00:00
Edward O'Callaghan
949850890f
Convert a few tests to FileCheck for PR5307.
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llvm-svn: 89584
2009-11-22 11:45:44 +00:00
Jim Grosbach
99c5b49c61
Revert 89562. We're being sneakier than I was giving us credit for, and this
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isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
Jim Grosbach
d4603a5c4e
Darwin requires a frame pointer for all non-leaf functions to support correct
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backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
Evan Cheng
9f57c4916e
Remat VLDRD from constpool. Clean up some instruction property specifications.
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llvm-svn: 89478
2009-11-20 19:57:15 +00:00
Evan Cheng
405012b096
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
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llvm-svn: 89423
2009-11-20 00:54:03 +00:00
Bob Wilson
70bfa110eb
Fix buildbots.
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llvm-svn: 89274
2009-11-18 23:30:38 +00:00
Bob Wilson
dccd3bdb4e
Tail duplication still needs to iterate. Duplicating new instructions onto
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the tail of a block may make that block a new candidate for duplication.
llvm-svn: 89264
2009-11-18 22:52:37 +00:00
Anton Korobeynikov
6b1a243be8
Forgot to commit test fixes
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llvm-svn: 89138
2009-11-17 20:38:36 +00:00
Jim Grosbach
1aa571da3c
Detect need for autoalignment of the stack earlier to catch spills more
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conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
Evan Cheng
9b46e74f42
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
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- If destination is a physical register and it has a subreg index, use the
sub-register instead.
This fixes PR5423.
llvm-svn: 88745
2009-11-14 02:55:43 +00:00
Evan Cheng
3781b2e7b3
Add radar number.
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llvm-svn: 88739
2009-11-14 02:11:32 +00:00
Evan Cheng
c56b0a0f14
Fix PR5412: Fix an inverted check and another missing sub-register check.
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llvm-svn: 88738
2009-11-14 02:09:09 +00:00
Evan Cheng
e2907b91de
Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers.
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llvm-svn: 88719
2009-11-13 23:16:41 +00:00
Evan Cheng
f629fdcab2
Fix PR5410: LiveVariables lost subreg def:
...
D0<def,dead> = ...
...
= S0<use, kill>
S0<def> = ...
...
D0<def> =
The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.
llvm-svn: 88690
2009-11-13 20:36:40 +00:00
Jim Grosbach
ea6c9c17f5
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
Anton Korobeynikov
30095499fc
It turns out that the testcase in question uncovered subreg-handling bug.
...
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
llvm-svn: 86375
2009-11-07 15:20:32 +00:00
Anton Korobeynikov
dca40933ee
Honour subreg machine operands during asmprinting
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llvm-svn: 86303
2009-11-06 23:45:15 +00:00
Bob Wilson
e79354a831
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
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will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
Evan Cheng
aaf30ce699
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
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llvm-svn: 86294
2009-11-06 22:24:13 +00:00
Dan Gohman
229f9edf7a
Update these tests for the new label names.
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llvm-svn: 86192
2009-11-05 23:31:40 +00:00
Bob Wilson
d14be3d83c
Attempt again to fix buildbot failures: make expected output less specific
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and compile with -mtriple to specify *-apple-darwin targets.
llvm-svn: 86081
2009-11-05 00:30:35 +00:00
Bob Wilson
9e30ecad4e
Fix broken test.
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llvm-svn: 86045
2009-11-04 20:04:11 +00:00
Bob Wilson
ca42ca296d
Add test for ARM indirectbr codegen.
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llvm-svn: 86042
2009-11-04 19:25:34 +00:00
Evan Cheng
caab17007b
fconsts / fconstd immediate should be proceeded with #.
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llvm-svn: 85952
2009-11-03 21:59:33 +00:00
Evan Cheng
d783406059
Re-apply 85799. It turns out my code isn't buggy.
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llvm-svn: 85947
2009-11-03 21:40:02 +00:00
Evan Cheng
ed22395c61
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
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llvm-svn: 85871
2009-11-03 05:52:54 +00:00
Anton Korobeynikov
48b30c79be
Revert r85049, it is causing PR5367
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llvm-svn: 85847
2009-11-03 00:24:48 +00:00
Evan Cheng
ca5847665b
Revert 85799 for now. It might be breaking llvm-gcc driver.
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llvm-svn: 85827
2009-11-02 21:49:14 +00:00