Sanjay Patel
ba0b11252c
don't repeat function names in comments; NFC
...
llvm-svn: 248166
2015-09-21 15:33:26 +00:00
Chad Rosier
432f88b93e
[Machine Combiner] Refactor machine reassociation code to be target-independent.
...
No functional change intended.
Patch by Haicheng Wu <haicheng@codeaurora.org>!
http://reviews.llvm.org/D12887
PR24522
llvm-svn: 248164
2015-09-21 15:09:11 +00:00
Artyom Skrobov
cfadb3d603
[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def
...
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a
hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with
a FIXME: attached.
This patch changes the handling of +t2dsp to be in line with other
architecture extensions.
Following review comments, also updating the description of FeatureDSPThumb2
in ARM.td.
Differential Revision: http://reviews.llvm.org/D12937
llvm-svn: 248152
2015-09-21 12:43:10 +00:00
Asaf Badouh
8011b4b495
[X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP
...
Differential Revision: http://reviews.llvm.org/D12524
llvm-svn: 248147
2015-09-21 10:23:53 +00:00
Daniel Sanders
819218ffe8
[mips] Allow constant expressions in second argument of .cpsetup.
...
Summary:
Also tightened up the test and made a trivial fix to prevent double-newline
after emitting .cpsetup directives.
Reviewers: vkalintiris
Subscribers: seanbruno, emaste, llvm-commits
Differential Revision: http://reviews.llvm.org/D12956
llvm-svn: 248143
2015-09-21 09:26:55 +00:00
Craig Topper
e3fc758778
Use makeArrayRef or None to avoid unnecessarily mentioning the ArrayRef type extra times. NFC
...
llvm-svn: 248140
2015-09-21 05:32:41 +00:00
Craig Topper
fd37494dd2
Don't pass StringRefs around by const reference. Pass by value instead per coding standards. NFC
...
llvm-svn: 248136
2015-09-21 00:18:00 +00:00
Craig Topper
280987c301
Cleanup places that passed SMLoc by const reference to pass it by value instead. NFC
...
llvm-svn: 248135
2015-09-20 23:35:59 +00:00
Sanjoy Das
ee4b307fb2
[IndVars] Use C++11 style field initialization; NFCI.
...
llvm-svn: 248131
2015-09-20 18:42:53 +00:00
Sanjoy Das
80655d90c3
[IndVars] Don't add a level of indentation for namespace {. NFC.
...
Whitespace-only change.
llvm-svn: 248130
2015-09-20 18:42:50 +00:00
Sanjay Patel
2feca45a6c
add test file ahead of any functional changes for PR22428
...
llvm-svn: 248123
2015-09-20 15:58:00 +00:00
Simon Pilgrim
162ca60e5b
[X86][SSE] Intrinsics builtins test refresh. NFCI
...
llvm-svn: 248122
2015-09-20 15:41:35 +00:00
Igor Breger
a833017e0d
AVX512: Implemented encoding and intrinsics for vcmpss/sd.
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12593
llvm-svn: 248121
2015-09-20 15:15:10 +00:00
Asaf Badouh
4ce11a0a36
[X86][AVX512] extend support in Scalar conversion
...
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics
Differential Revision: http://reviews.llvm.org/D12665
llvm-svn: 248117
2015-09-20 14:31:19 +00:00
Igor Breger
6c78cd17ac
AVX512: vsqrtss/sd encoding and intrinsics implementation.
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D12102
llvm-svn: 248116
2015-09-20 09:13:41 +00:00
Asaf Badouh
981ab82bef
[X86][AVX512DQ] Add fpclass instruction
...
Differential Revision: http://reviews.llvm.org/D12931
llvm-svn: 248115
2015-09-20 08:46:07 +00:00
Michael Kuperstein
516836f0c5
[X86] Fix sitofp and uitofp instruction matching failures with long double and avx512
...
The operation action for i32 and i64 cannot be set to legal, as long double
needs custom lowering.
Patch by: mitch.l.bodart@intel.com
Differential Revision: http://reviews.llvm.org/D12372
llvm-svn: 248114
2015-09-20 08:12:17 +00:00
Igor Breger
5be1c75e87
AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, vshufi32x4
...
Added tests for intrinsics.
Differential Revision: http://reviews.llvm.org/D12525
llvm-svn: 248113
2015-09-20 07:18:53 +00:00
Sanjoy Das
ddd0454eef
[IndVars] Don't repeat function names in comment; NFC.
...
Only changes comments.
llvm-svn: 248112
2015-09-20 06:58:03 +00:00
Igor Breger
43e0d98a01
AVX512: Implement instructions encoding, lowering and intrinsics
...
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.
Differential Revision: http://reviews.llvm.org/D11893
llvm-svn: 248111
2015-09-20 06:52:42 +00:00
Saleem Abdulrasool
e7f4599d69
ARM: cleanup formatting
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clang-format a line which was poorly formatted. NFC.
llvm-svn: 248110
2015-09-20 03:19:09 +00:00
Sanjoy Das
1b1e9a5dc4
[IndVars] Fix a bug in r248045.
...
Because -indvars widens induction variables through arithmetic,
`NeverNegative` cannot be a property of the `WidenIV` (a `WidenIV`
manages information for all transitive uses of an IV being widened,
including uses of `-1 * IV`). Instead it must live on `NarrowIVDefUse`
which manages information for a specific def-use edge in the transitive
use list of an induction variable.
This change also adds a test case that demonstrates the problem with
r248045.
llvm-svn: 248107
2015-09-20 01:52:18 +00:00
Davide Italiano
d2d6cb55fa
Fixup r248096, commit the *correct* test.
...
llvm-svn: 248097
2015-09-19 20:52:47 +00:00
Davide Italiano
0f09710333
[obj2yaml] Fix "time of check to time of use" bug. Add a test.
...
llvm-svn: 248096
2015-09-19 20:49:34 +00:00
Simon Pilgrim
3684c48547
[X86][AVX2] Use general sext IR for vpmovsx stack folding tests
...
llvm-svn: 248093
2015-09-19 17:04:18 +00:00
Simon Pilgrim
353a09ac7f
[X86][SSE] Vectorize CTTZ + CTTZ_ZERO_UNDEF
...
Now that we have fast vector CTPOP implementations we can use this to speed up vector CTTZ using the pattern (cttz(x) = ctpop((x & -x) - 1))
Additionally, for AVX512CD that provides lzcnt instructions we can use the pattern (cttz_undef(x) = (width - 1) - ctlz(x & -x))
Differential Revision: http://reviews.llvm.org/D12663
llvm-svn: 248091
2015-09-19 13:22:57 +00:00
Simon Pilgrim
9664e19104
[InstCombine] Use SimplifyDemandedVectorEltsLow helper function. NFCI.
...
Use the SimplifyDemandedVectorEltsLow helper function introduced in D12680.
llvm-svn: 248089
2015-09-19 11:41:53 +00:00
NAKAMURA Takumi
243cdd01c7
[CMake] Update LLVM_TEST_DEPENDS not to use macho-dump. It has been unused since r247235.
...
llvm-svn: 248088
2015-09-19 07:19:30 +00:00
Matt Arsenault
b9aeee466c
AMDGPU: Remove dead code
...
getCFGStructurizerRegClass is not used for SI, so
move it into R600 specific stuff.
llvm-svn: 248087
2015-09-19 06:41:10 +00:00
Bob Wilson
bcfd90d843
NFC: Fix indentation and add braces to clarify nested of else-statement.
...
llvm-svn: 248086
2015-09-19 06:20:59 +00:00
Maksim Panchenko
2b928f8ca1
[PrologEpilogInserter] Minor refactoring.
...
Differential Revision: http://reviews.llvm.org/D12924
llvm-svn: 248084
2015-09-19 04:42:15 +00:00
Maksim Panchenko
ec316af1f7
Test commit. Fix comment. NFC.
...
llvm-svn: 248082
2015-09-19 04:01:19 +00:00
David Majnemer
906a17fb34
[InstCombine] FoldICmpCstShrCst failed for ashr when comparing against -1
...
(icmp eq (ashr C1, %V) -1) may have multiple answers if C1 is not a
power of two and has the sign bit set.
This fixes PR24873.
llvm-svn: 248074
2015-09-19 00:48:31 +00:00
David Majnemer
d15737b6a9
[InstCombine] FoldICmpCstShrCst didn't handle icmps of -1 in the ashr case correctly
...
llvm-svn: 248073
2015-09-19 00:48:26 +00:00
Matt Arsenault
bd7c6a697f
AMDGPU: Add failing testcase for live interval construction
...
llvm-svn: 248067
2015-09-19 00:03:56 +00:00
Sanjoy Das
3f75be72a8
[IndVars] Widen more comparisons for non-negative induction vars
...
Summary:
If an induction variable is provably non-negative, its sign extension is
equal to its zero extension. This means narrow uses like
icmp slt iNarrow %indvar, %rhs
can be widened into
icmp slt iWide zext(%indvar), sext(%rhs)
Reviewers: atrick, mcrosier, hfinkel
Subscribers: hfinkel, reames, llvm-commits
Differential Revision: http://reviews.llvm.org/D12745
llvm-svn: 248045
2015-09-18 21:21:02 +00:00
Luke Larson
e3de9f740c
Fix typo and test commit
...
llvm-svn: 248042
2015-09-18 21:15:45 +00:00
Rafael Espindola
e32f04d220
This code never uses r_addend, so it can just use Elf_Rel.
...
llvm-svn: 248040
2015-09-18 21:12:38 +00:00
Chris Bieneman
002bf95a73
[CMake] Adding ALWAYS_GENERATE option to symlink utility functions.
...
This implements the behavior required for clang symlinks which should be always generated.
llvm-svn: 248039
2015-09-18 21:08:32 +00:00
Davide Italiano
3069215616
[Object/ELF] Change comment to reflect reality.
...
llvm-svn: 248032
2015-09-18 20:41:15 +00:00
Cong Hou
502353740b
Update edge weights properly when merging blocks in if-conversion.
...
In if-conversion, there is a utility function MergeBlocks() that is used to merge blocks. However, when new edges are built in this function the edge weight is either not provided or not updated properly, leading to a modified CFG with incorrect edge weights. This patch corrects this issue.
Differential Revision: http://reviews.llvm.org/D12513
llvm-svn: 248030
2015-09-18 20:22:41 +00:00
Eric Christopher
382e31afae
Limit the range of processors supported by ARM fast isel to v6 or
...
later as that's all that is tested right now.
Fixes PR24858.
llvm-svn: 248027
2015-09-18 20:08:18 +00:00
Teresa Johnson
b5092973af
Remove couple of new Bitcode enum vals that snuck in via r247927 (NFC)
...
These are meant to be part of the follow on patch I am sending for
review shortly.
llvm-svn: 248023
2015-09-18 19:38:53 +00:00
Larisse Voufo
d25582bd2b
Clean up: Refactoring the hardcoded value of 6 for FindAvailableLoadedValue()'s parameter MaxInstsToScan. (Complete version of r247497. See D12886)
...
llvm-svn: 248022
2015-09-18 19:14:35 +00:00
James Y Knight
6a6ee2cd7f
Make MachineScheduler debug output less confusing.
...
At least...a little bit.
llvm-svn: 248020
2015-09-18 18:52:20 +00:00
Cong Hou
7856c96129
Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are scaled by a probability to avoid precision issue.
...
In ARMBaseInstrInfo::isProfitableToIfCvt(), there is a simple cost model in which the number of cycles is scaled by a probability to estimate the cost. However, when the number of cycles is small (which is usually the case), there is a precision issue after the computation. To avoid this issue, this patch scales those cycles by 1024 (chosen to make the multiplication a litter faster) before they are scaled by the probability. Other variables are also scaled up for the final comparison.
Differential Revision: http://reviews.llvm.org/D12742
llvm-svn: 248018
2015-09-18 18:19:40 +00:00
Matthias Braun
9b1349ccd2
SelectionDAGDumper: Leave out the <multiple use> markers
...
They mostly clutter the output while it is still possible to see which
node has multiple users without them.
Differential Revision: http://reviews.llvm.org/D12569
llvm-svn: 248013
2015-09-18 17:57:33 +00:00
Matthias Braun
f88f436e85
SelectionDAGDumper: Avoid unnecessary newlines
...
Before:
t0 = EntryToken:ch
t0: <multiple use>
t0: <multiple use>
t1 = CopyFromReg:v4f32,ch t0, Register:v4f32 %vreg0
t25 = IMPLICIT_DEF:v4f32
t26 = HADDPSrr:v4f32 t1, t25
t23 = CopyToReg:ch,glue t0, Register:v4f32 %XMM0, t26
t23: <multiple use>
t23: <multiple use>
t24 = RETQ:ch Register:v4f32 %XMM0, t23, t23:1
After:
t0: <multiple use>
t0: <multiple use>
t1 = CopyFromReg:v4f32,ch t0, Register:v4f32 %vreg0
t26 = X86ISD::FHADD:v4f32 t1, undef:v4f32
t23 = CopyToReg:ch,glue t0, Register:v4f32 %XMM0, t26
t23: <multiple use>
t21 = TargetConstant:i16<0>
t23: <multiple use>
t24 = X86ISD::RET_FLAG:ch t23, t21, Register:v4f32 %XMM0, t23:1
Differential Revision: http://reviews.llvm.org/D12568
llvm-svn: 248012
2015-09-18 17:57:31 +00:00
Matthias Braun
85bc1d4ef5
SelectionDAGDumper: Hide [ID=X], [ORD=X] and source locations by default.
...
You can show them with the new -dag-dump-verbose switch.
Differential Revision: http://reviews.llvm.org/D12566
llvm-svn: 248011
2015-09-18 17:57:28 +00:00
Matthias Braun
8bd54b9028
SelectionDAG: Introduce PersistentID to SDNode for assert builds.
...
This gives us more human readable numbers to identify nodes in debug
dumps.
Before:
0x7fcbd9700160: ch = EntryToken
0x7fcbd985c7c8: i64 = Register %RAX
...
0x7fcbd9700160: <multiple use>
0x7fcbd985c578: i64,ch = MOV64rm 0x7fcbd985c6a0, 0x7fcbd985cc68, 0x7fcbd985c200, 0x7fcbd985cd90, 0x7fcbd985ceb8, 0x7fcbd9700160<Mem:LD8[@foo]> [ORD=2]
0x7fcbd985c8f0: ch,glue = CopyToReg 0x7fcbd9700160, 0x7fcbd985c7c8, 0x7fcbd985c578 [ORD=3]
0x7fcbd985c7c8: <multiple use>
0x7fcbd985c8f0: <multiple use>
0x7fcbd985c8f0: <multiple use>
0x7fcbd985ca18: ch = RETQ 0x7fcbd985c7c8, 0x7fcbd985c8f0, 0x7fcbd985c8f0:1 [ORD=3]
Now:
t0: ch = EntryToken
t5: i64 = Register %RAX
...
t0: <multiple use>
t3: i64,ch = MOV64rm t10, t12, t11, t13, t14, t0<Mem:LD8[@foo]> [ORD=2]
t6: ch,glue = CopyToReg t0, t5, t3 [ORD=3]
t5: <multiple use>
t6: <multiple use>
t6: <multiple use>
t7: ch = RETQ t5, t6, t6:1 [ORD=3]
Differential Revision: http://reviews.llvm.org/D12564
llvm-svn: 248010
2015-09-18 17:41:00 +00:00