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e2b20a3526
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1073 Commits

Author SHA1 Message Date
Jim Grosbach
e2b20a3526 PR2985 / <rdar://problem/6584986> 
When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.

llvm-svn: 68545
 2009-04-07 20:34:09 +00:00
Chris Lattner
b2dd43e8dd "This adds a getName() method to TargetRegisterClass, just like in TargetRegisterInfo. 
This makes debugging register classes a bit easier."

Patch by Jakob Stoklund Olesen!

llvm-svn: 68400
 2009-04-03 20:25:41 +00:00
Dan Gohman
f431de416e Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused. 
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.

llvm-svn: 68355
 2009-04-03 00:25:26 +00:00
Anton Korobeynikov
0404baca28 Do not propagate ELF-specific stuff (data.rel) into other targets. This simplifies code and also ensures correctness. 
llvm-svn: 68032
 2009-03-30 15:27:43 +00:00
Anton Korobeynikov
2ea565a37b Add data.rel stuff 
llvm-svn: 68031
 2009-03-30 15:27:03 +00:00
Anton Korobeynikov
ec131d94ff Honour relocation behaviour stuff for ro objects 
llvm-svn: 68005
 2009-03-29 17:13:49 +00:00
Arnold Schwaighofer
636127325b Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1). 
llvm-svn: 67934
 2009-03-28 08:33:27 +00:00
Evan Cheng
a15fdaa292 Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g. 
x * 40
=>
shlq    $3, %rdi
leaq    (%rdi,%rdi,4), %rax

This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq    (%rdi,%rdi,2), %rax
leaq    (%rsi,%rax,8), %rax

llvm-svn: 67917
 2009-03-28 05:57:29 +00:00
Evan Cheng
3a7489a4cc CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose. 
llvm-svn: 67668
 2009-03-25 01:47:28 +00:00
Mon P Wang
6ac3a9ac9d Added option to enable generating less precise mad (multiply addition) 
for those architectures that support the instruction.

llvm-svn: 67363
 2009-03-20 05:06:58 +00:00
Bill Wendling
fca05e3a5c Add a -no-implicit-float flag. This acts like -soft-float, but may generate 
floating point instructions that are explicitly specified by the user.

llvm-svn: 66719
 2009-03-11 22:30:01 +00:00
Dan Gohman
51d4e8db6a Fix a bunch of Doxygen syntax issues. Escape special characters, 
and put @file directives on their own comment line.

llvm-svn: 65920
 2009-03-03 02:55:14 +00:00
Rafael Espindola
880e63bf01 Refactor TLS code and add some tests. The tests and expected results are: 
pic |  declaration | linkage  | visibility |

!pic |  declaration | external | default    | tls1.ll     tls2.ll     | local exec
 pic |  declaration | external | default    | tls1-pic.ll tls2-pic.ll | general dynamic
!pic | !declaration | external | default    | tls3.ll     tls4.ll     | initial exec
 pic | !declaration | external | default    | tls3-pic.ll tls4-pic.ll | general dynamic

!pic |  declaration | external | hidden     | tls7.ll     tls8.ll     | local exec
 pic |  declaration | external | hidden     | X                       | local dynamic
!pic | !declaration | external | hidden     | tls9.ll     tls10.ll    | local exec
 pic | !declaration | external | hidden     | X                       | local dynamic

!pic |  declaration | internal | default    | tls5.ll     tls6.ll     | local exec
 pic |  declaration | internal | default    | X                       | local dynamic

The ones marked with an X have not been implemented since local dynamic is not implemented.

llvm-svn: 65632
 2009-02-27 13:37:18 +00:00
Mon P Wang
c9b4dab417 Added support to have TableGen provide information if an intrinsic (core 
or target) can be overloaded or not.

llvm-svn: 65404
 2009-02-24 23:17:49 +00:00
Dale Johannesen
bd87541147 Describe tail merging's use of InsertBranch. 
llvm-svn: 65062
 2009-02-19 19:40:21 +00:00
Nate Begeman
5e78e558ff Add support to the JIT for true non-lazy operation. When a call to a function 
that has not been JIT'd yet, the callee is put on a list of pending functions
to JIT.  The call is directed through a stub, which is updated with the address
of the function after it has been JIT'd.  A new interface for allocating and
updating empty stubs is provided.

Add support for removing the ModuleProvider the JIT was created with, which
would otherwise invalidate the JIT's PassManager, which is initialized with the
ModuleProvider's Module.

Add support under a new ExecutionEngine flag for emitting the infomration 
necessary to update Function and GlobalVariable stubs after JITing them, by
recording the address of the stub and the name of the GlobalValue.  This allows
code to be copied from one address space to another, where libraries may live
at different virtual addresses, and have the stubs updated with their new
correct target addresses.

llvm-svn: 64906
 2009-02-18 08:31:02 +00:00
Dan Gohman
0e73582689 Eliminate several more unnecessary intptr_t casts. 
llvm-svn: 64888
 2009-02-18 05:09:16 +00:00
Evan Cheng
9dc1507838 Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty 
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.

llvm-svn: 64124
 2009-02-09 07:14:22 +00:00
Dan Gohman
4105a38248 Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowing 
ScheduleDAG's TLI member to use const.

llvm-svn: 64018
 2009-02-07 16:15:20 +00:00
Evan Cheng
4ff40adb90 We don't really need the abort here. This unbreak x86_64 linux build. 
llvm-svn: 63940
 2009-02-06 17:51:34 +00:00
Evan Cheng
e00df1d39c Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. 
llvm-svn: 63938
 2009-02-06 17:43:24 +00:00
Evan Cheng
381b2df5ff Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. 
llvm-svn: 63936
 2009-02-06 17:17:30 +00:00
Evan Cheng
629b2b88c9 Change -1 => negative number. 
llvm-svn: 63935
 2009-02-06 17:12:56 +00:00
Evan Cheng
d663d7a7c1 Document the meaning of -1 for getCopyCost. 
llvm-svn: 63933
 2009-02-06 17:01:33 +00:00
Evan Cheng
15495e1cfe Clarify comments. 
llvm-svn: 63851
 2009-02-05 08:41:53 +00:00
Dale Johannesen
fa28929927 Reapply 63765. Patches for clang and llvm-gcc to follow. 
llvm-svn: 63812
 2009-02-05 01:49:45 +00:00
Dale Johannesen
f6e1822ccd Reverting 63765. This broke the build of both clang 
and llvm-gcc.

llvm-svn: 63786
 2009-02-04 22:47:25 +00:00
Nate Begeman
66f10b55ed New feature: add support for target intrinsics being defined in the 
target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.

llvm-svn: 63765
 2009-02-04 19:47:21 +00:00
Chris Lattner
2291a8be5e add a friend needed by a stringmap change. 
llvm-svn: 63706
 2009-02-04 01:51:53 +00:00
Dale Johannesen
b7f2857776 Add some DL propagation to places that didn't 
have it yet.  More coming.

llvm-svn: 63673
 2009-02-03 22:26:09 +00:00
Dale Johannesen
84498c427e Propagation in TargetLowering. Includes passing a DL 
into SimplifySetCC which gets called elsewhere.

llvm-svn: 63583
 2009-02-03 00:47:48 +00:00
Sanjiv Gupta
c47a19b23e Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in non-default address spaces. 
llvm-svn: 63521
 2009-02-02 16:53:06 +00:00
Dale Johannesen
7eb7de0393 Fix build on case-sensitive filesystems (i.e. everybody else) 
llvm-svn: 63448
 2009-01-30 23:20:42 +00:00
Dale Johannesen
39738b1ff8 Make LowerCallTo and LowerArguments take a DebugLoc 
argument.  Adjust all callers and overloaded versions.

llvm-svn: 63444
 2009-01-30 23:10:59 +00:00
Sanjiv Gupta
e442452ade Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces. 
llvm-svn: 63377
 2009-01-30 04:25:10 +00:00
Dan Gohman
9d120d6d8f Make x86's BT instruction matching more thorough, and add some 
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266
 2009-01-29 01:59:02 +00:00
Dan Gohman
bc43253a91 Make isOperationLegal do what its name suggests, and introduce a 
new isOperationLegalOrCustom, which does what isOperationLegal
previously did.

Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.

This is for the second half of PR3376.

llvm-svn: 63212
 2009-01-28 17:46:25 +00:00
Scott Michel
56fa9ba0b6 Make the Dwarf macro information section optional; CellSPU's assembler 
doesn't support it. The default is set to 'true', so this should not
impact any other target backends.

llvm-svn: 63058
 2009-01-26 22:32:51 +00:00
Dan Gohman
3a51d8e847 Implement Red Zone utilization on x86-64. This is currently 
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.

llvm-svn: 63056
 2009-01-26 22:22:31 +00:00
Evan Cheng
7cdc6e4f8c Cross register class coalescing. Not yet enabled. 
llvm-svn: 62832
 2009-01-23 02:15:19 +00:00
Evan Cheng
c971801ae1 Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
llvm-svn: 62762
 2009-01-22 09:10:11 +00:00
Duncan Sands
392dc77fc6 Cleanup whitespace and comments, and tweak some 
prototypes, in operand type legalization.  No
functionality change.

llvm-svn: 62680
 2009-01-21 09:00:29 +00:00
Sanjiv Gupta
074553c4fb Allow targets to legalize operations (with illegal operands) that produces multiple values. For example, a load with an illegal operand (a load produces two values, a value and chain). 
llvm-svn: 62663
 2009-01-21 04:48:39 +00:00
Evan Cheng
b3c82db63d Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 
llvm-svn: 62600
 2009-01-20 19:12:24 +00:00
Mikhail Glushenkov
49be18cfc6 Registry.h should not depend on CommandLine.h. 
Split Support/Registry.h into two files so that we have less to
recompile every time CommandLine.h is changed.

llvm-svn: 62312
 2009-01-16 07:02:28 +00:00
Mikhail Glushenkov
5000223556 Delete trailing whitespace. 
llvm-svn: 62307
 2009-01-16 06:53:46 +00:00
Dan Gohman
37d7b5be33 Make getWidenVectorType const. 
llvm-svn: 62265
 2009-01-15 17:34:08 +00:00
Dan Gohman
ab89b888e8 Const-qualify getPreIndexedAddressParts and friends. 
llvm-svn: 62259
 2009-01-15 16:29:45 +00:00
Devang Patel
eed0505ed8 Use DebugInfo interface to lower dbg_* intrinsics. 
llvm-svn: 62127
 2009-01-13 00:35:13 +00:00
Duncan Sands
bcdbfb63dc Rename getABITypeSize to getTypePaddedSize, as 
suggested by Chris.

llvm-svn: 62099
 2009-01-12 20:38:59 +00:00