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Commit Graph

206853 Commits

Author SHA1 Message Date
Florian Hahn
e2fe6ad000 [IRGen] Add !annotation metadata for auto-init stores.
This patch updates Clang's IRGen to add !annotation nodes with an
"auto-init" annotation to all stores for auto-initialization.

As discussed in 'RFC: Combining Annotation Metadata and Remarks'
(http://lists.llvm.org/pipermail/llvm-dev/2020-November/146393.html)
this allows using optimization remarks to track down where auto-init
code was inserted (and not removed by optimizations).

There are a few cases in the tests where !annotation gets dropped by
optimizations. Those optimizations will be updated in subsequent
patches.

This patch is based on a patch by Francis Visoiu Mistrih.

Reviewed By: thegameg, paquette

Differential Revision: https://reviews.llvm.org/D91417
2020-11-16 10:37:02 +00:00
Sjoerd Meijer
70ae328422 [LoopFlatten] Widen the IV
Widen the IV to the widest available and legal integer type, which makes this
transformations always safe so that we can skip overflow checks.

Motivation is to let this pass trigger on 64-bit targets too, and this is the
last patch in a serie to achieve this: D90402 moves pass LoopFlatten to just
before IndVarSimplify so that IVs are not already widened, D90421 factors out
widening from IndVarSimplify into Utils/SimplifyIndVar so that we can also use
it in LoopFlatten.

Differential Revision: https://reviews.llvm.org/D90640
2020-11-16 10:20:13 +00:00
David Penry
f9366e87d8 [ARM] Cortex-M7 schedule
This patch adds the SchedMachineModel for Cortex-M7. It
also adds test cases for the scheduling information.

Details of the pipeline and descriptions are in comments
in file ARMScheduleM7.td included in this patch.

Differential Revision: https://reviews.llvm.org/D91355
2020-11-16 10:16:07 +00:00
Fraser Cormack
15982c1bb7 [RISCV] Use a macro to simplify getTargetNodeName
Similar to the X86 and AMDGPU targets, this uses a macro to cut down on
repetitive and error-prone code when converting RISCVISD node names to
strings in getTargetNodeName.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D91414
2020-11-16 09:33:47 +00:00
Kazushi (Jam) Marukawa
b6b0af3190 [VE] Change variable capitalization
Change dl to DL in VEFrameLowering.cpp.  And clean some comments.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91490
2020-11-16 18:25:23 +09:00
Simon Moll
28f80af0cf [VP][NFC] Rename to HANDLE_VP_TO_OPC
Use the less surprising shorthand OPC instead of OC.
2020-11-16 10:24:18 +01:00
Jan Svoboda
f2ea1a89f7 [clang][cli] Add support for options with two flags for controlling the same field.
This enables automatically parsing and generating CC1 arguments for options where two flags control the same field, e.g. -fexperimental-new-pass-manager and -fno-experimental new pass manager.

Reviewed By: Bigcheese, dexonsmith

Original patch by Daniel Grumberg.

Differential Revision: https://reviews.llvm.org/D83071
2020-11-16 10:21:54 +01:00
Lang Hames
460e0b8ba2 [MCJIT] Profile the code generated by MCJIT engine using Intel VTune profiler
Patch by Elena Kovanova. Thanks Elena!

Problem:

LLVM already has a feature to profile the JIT-compiled code with VTune. This is
done using Intel JIT Profiling API (https://github.com/intel/ittapi). Function
information is captured by VTune as soon as the function is JIT-compiled. We
tried to use the same approach to report the function information generated by
the MCJIT engine – read parsing the debug information for in-memory ELF module
and report it using JIT API. As the results, we figured out that it did not work
properly for the following cases: inline functions, the functions located in
multiple source files, the functions having several bodies (address ranges).

Solution:

To overcome limitations described above, we have introduced new APIs as a part
of Intel ITT APIs to report the entire in-memory ELF module to be further
processed as regular ELF binaries with debug information.

This patch

1. Switches LLVM to open source version of Intel ITT/JIT APIs
(https://github.com/intel/ittapi) to keep it always up to date.

2. Adds support of profiling the code generated by MCJIT engine using Intel
VTune profiler

Another separate patch will get rid of obsolete Intel ITT APIs stuff, having
LLVM already switched to https://github.com/intel/ittapi.

Differential Revision: https://reviews.llvm.org/D86435
2020-11-16 19:28:14 +11:00
Simon Moll
4b7f9fd6c6 [VE] LVLGen sets VL before vector insts
The VE backend represents vector instructions with an explicit 'i32'
vector length operand.  In the VE ISA, the vector length is always read
from the VL hardware register.  The LVLGen pass inserts 'lvl'
instructions as necessary to set VL to the right value before each
vector instruction.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D91416
2020-11-16 09:19:14 +01:00
Max Kazantsev
55b8c19420 Recommit "[NFC] Move code between functions as a preparation step for further improvement"
The bug should be fixed now.
2020-11-16 14:30:34 +07:00
Kazu Hirata
000e21d54d [JumpThreading] Call eraseBlock when folding a conditional branch
This patch teaches the jump threading pass to call BPI->eraseBlock
when it folds a conditional branch.

Without this patch, BranchProbabilityInfo could end up with stale edge
probabilities for the basic block containing the conditional branch --
one edge probability with less than 1.0 and the other for a removed
edge.

This patch is one of the steps before we can safely re-apply D91017.

Differential Revision: https://reviews.llvm.org/D91511
2020-11-15 22:29:30 -08:00
Kazu Hirata
a80ed1a2ff [IR] Use llvm::is_contained in BasicBlock::removePredecessor (NFC) 2020-11-15 21:15:31 -08:00
Kazu Hirata
c8d95494fa [Loop Fusion] Use pred_empty and succ_empty (NFC) 2020-11-15 20:32:57 -08:00
Kazu Hirata
ab8dbdfb7d [ADCE] Use succ_empty (NFC) 2020-11-15 19:52:59 -08:00
QingShan Zhang
4b6ca2076d [NFC][Test] Add test coverage for IEEE Long Double on Power8 2020-11-16 03:45:51 +00:00
Kazu Hirata
b19e46e051 [BranchProbabilityInfo] Use predecessors(BB) and successors(BB) (NFC) 2020-11-15 19:26:38 -08:00
Kazu Hirata
ec77f903c9 [TRE] Use successors(BB) (NFC) 2020-11-15 19:12:49 -08:00
Craig Topper
255f4af3b1 [X86] Fix crash with i64 bitreverse on 32-bit targets with XOP.
We unconditionally marked i64 as Custom, but did not install a
handler in ReplaceNodeResults when i64 isn't legal type. This
leads to ReplaceNodeResults asserting.

We have two options to fix this. Only mark i64 as Custom on
64-bit targets and let it expand to two i32 bitreverses which
each need a VPPERM. Or the other option is to add the Custom
handling to ReplaceNodeResults. This is what I went with.
2020-11-15 19:02:34 -08:00
Kazu Hirata
16475efc18 [SanitizerCoverage] Use llvm::all_of (NFC) 2020-11-15 19:01:20 -08:00
Serguei Katkov
fb8d2c2300 [IRCE] Use the same min runtime iteration threshold for BPI and BFI checks
In the last change to IRCE the BPI is ignored if BFI is present, however
BFI and BPI have a different thresholds. Specifically BPI approach checks only
latch exit probability so it is expected if the loop has only one exit block (latch)
the behavior with BFI and BPI should be the same,

BPI approach by default uses threshold 10, so it considers the loop with estimated
number of iterations less then 10 should not be considered for IRCE optimization.
BFI approach uses the default value 3 and this is inconsistent.

The CL modifies the code to use the same threshold for both approaches..

The test is updated due to it has two side-exits (except latch) and each of them has a
probability 1/16, so BFI estimates the number of runtime iteration is about to 7
(1/16 + 1/16 + some for latch) and test fails.

Reviewers: mkazantsev, ebrevnov
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D91230
2020-11-16 09:21:50 +07:00
Wang, Pengfei
c275334e12 [CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
I had manually removed unused prefixes from CodeGen/X86 directory for more than 100 tests.
I checked the change history for each of them at the beginning, and then I mainly focused on the format since I found all of the unused prefixes were result from either insensible copy or residuum after functional update.
I think it's OK to remove the remaining X86 tests by script now. I wrote a rough script which works for me in most tests. I put it in llvm/utils temporarily for review and hope it may help other components owners.
The tests in this patch are all generated by the tool and checked by update tool for the autogenerated tests. I skimmed them and checked about 30 tests and didn't find any unexpected changes.

Reviewed By: mtrofin, MaskRay

Differential Revision: https://reviews.llvm.org/D91496
2020-11-16 09:45:55 +08:00
Sanjay Patel
7c86a73d6a [InstCombine] reduce code for flip of masked bit; NFC
There are 1-2 potential follow-up NFC commits to reduce
this further on the way to generalizing this for vectors.

The operand replacing path should be dead code because demanded
bits handles that more generally (D91415).
2020-11-15 15:43:34 -05:00
Sanjay Patel
77f50978dd [InstCombine] add multi-use demanded bits fold for add with low-bit mask
I noticed an add example like the one from D91343, so here's a similar patch.
The logic is based on existing code for the single-use demanded bits fold.
But I only matched a constant instead of using compute known bits on the
operands because that was the motivating patterni that I noticed.

I think this will allow removing a special-case (but incomplete) dedicated
fold within visitAnd(), but I need to untangle the existing code to be sure.

https://rise4fun.com/Alive/V6fP

  Name: add with low mask
  Pre: (C1 & (-1 u>> countLeadingZeros(C2))) == 0
  %a = add i8 %x, C1
  %r = and i8 %a, C2
  =>
  %r = and i8 %x, C2

Differential Revision: https://reviews.llvm.org/D91415
2020-11-15 15:09:49 -05:00
Sanjay Patel
c801e0e7bd [InstCombine] add vector tests for multi-use demanded bits; NFC
See D91415.
2020-11-15 15:09:49 -05:00
Nikita Popov
ccce9f99c5 [AA] Add missing AAQI parameter
This alias() call did not pass on the AAQueryInfo.
2020-11-15 20:29:53 +01:00
Florian Hahn
a34e7402ed [MemorySSA] Add pointer decrement loop clobber test case. 2020-11-15 18:00:01 +00:00
Florian Hahn
df302df8f2 [VPlan] Use VPValue def for VPWidenGEPRecipe.
This patch turns VPWidenGEPRecipe into a VPValue and uses it
during VPlan construction and codegeneration instead of the plain IR
reference where possible.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D84683
2020-11-15 15:12:47 +00:00
Paul C. Anagnostopoulos
af5277fb13 [TableGen] Improve a couple of descriptions in the command guide
Differential Revision: https://reviews.llvm.org/D91484
2020-11-15 09:59:59 -05:00
Nikita Popov
9dd51839f7 Revert "[SCEV] Factor out part of wrap flag detection logic [NFC-ish]"
This reverts commit 1ec6e1eb8a084bffae8a40236eb9925d8026dd07.

This change causes a significant compile-time regression:
https://llvm-compile-time-tracker.com/compare.php?from=dd0b8b94d0796bd895cc998dd163b4fbebceb0b8&to=1ec6e1eb8a084bffae8a40236eb9925d8026dd07&stat=instructions

I assume that this is due to the non-NFC part of the change, which
now performs expensive nowrap inference even for nowrap flags that
are not used by the particular code.
2020-11-15 10:19:44 +01:00
Philip Reames
3c9c657cb9 [SCEV] Factor out part of wrap flag detection logic [NFC-ish]
In an effort to make code around flag determination more readable, and (possibly) prepare for a follow up change, factor out some of the flag detection logic.  In the process, reduce the number of locations we mutate wrap flags by a couple.

Note that this isn't NFC.  The old code tried for NSW xor (NUW || NW).  This is, two different paths computed different sets of wrap flags.  The new code will try for all three.  The result is that some expressions end up with a few extra flags set.
2020-11-14 19:21:05 -08:00
Arthur Eubanks
9df829612b [DCE] Port -redundant-dbg-inst-elim to NPM
This is used to test RemoveRedundantDbgInstrs(), which is used by other
passes.

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D91477
2020-11-14 16:55:20 -08:00
Florian Hahn
19840b7955 Recommit "[VPlan] Use VPValue def for VPWidenSelectRecipe."
This reverts the revert commit c8d73d939fa4fda9c87b3979225d02d63062bd68.

It includes a fix for cases where we missed inserting VPValues
for some selects, which should fix PR48142.
2020-11-14 20:00:25 +00:00
David Green
ce6cf752cd [AArch64] Remove unused check prefixes. NFC 2020-11-14 18:30:17 +00:00
Paul C. Anagnostopoulos
151d493181 [TableGen] Fix missing braces in if statement 2020-11-14 12:38:44 -05:00
Mehdi Amini
75727d2f3e Fix build (ninja check without running ninja first)
9218ff50f9 removed the BUILD.txt file, and as a subtle side-effect
libLLVMFrontendOpenACC wasn't a dependency of `ninja check` anymore.
However llvm-config requires all components to be built, and the
relevant test is broken when libLLVMFrontendOpenACC isn't built.

Unittest for libLLVMFrontendOpenACC are pending, but this addition
should fix some bots in the meantime.
2020-11-14 16:57:28 +00:00
Nathan James
0973aff95b [llvm][NFC] Remove unnecessary vector creation in Annotations 2020-11-14 15:55:09 +00:00
Nikita Popov
7c3186ef2c [BasicAA] Remove unnecessary size limitation
We're dropping a common offset from both GEPs here. It's not
necessary for the access sizes to be the same as well.
2020-11-14 16:51:31 +01:00
David Green
b34da80b48 [ARM] Remove more unused check prefixes, NFC 2020-11-14 15:37:53 +00:00
Nico Weber
02db4f902b Fix build after 54f9ee334 2020-11-14 10:23:22 -05:00
Nico Weber
106408c120 [gn build] (manually) merge e51631ca4cf 2020-11-14 10:12:15 -05:00
Paul C. Anagnostopoulos
17cd31c30e [TableGen] Add frontend/backend phase timing capability.
Describe in the BackEnd Developer's Guide. Instrument a few backends.

Remove an old unused timing facility. Add a null backend for timing
the parser.

Differential Revision: https://reviews.llvm.org/D91388
2020-11-14 10:10:29 -05:00
Sanjay Patel
47294cfe00 [CostModel] make default size cost for libcalls small (again)
This was changed recently with D90554 / f7eac51b9b3f
...because we had a regression testing blindspot for intrinsics
that are expected to be lowered to libcalls.

In general, we want the *size* cost for a scalar call to be cheap
even if the other costs are expensive - we expect it to just be
a branch with some optional stack manipulation.

It is likely that we will want to carve out some
exceptions/overrides to this rule as follow-up patches for
calls that have some general and/or target-specific difference
to the expected lowering.

This was noticed as a regression in unrolling, so we have a test
for that now along with a couple of direct cost model tests.

If the assumed scalarization costs for the oversized vector
calls are not realistic, that would be another follow-up
refinement of the cost models.
2020-11-14 08:15:35 -05:00
Sanjay Patel
1fb5766336 [CostModel] add tests for math library calls; NFC 2020-11-14 08:15:35 -05:00
Arnold Schwaighofer
2537f5b63c [Coroutines] Make sure that async coroutine context size is a multiple of the alignment requirement
This simplifies the code the allocator has to executed

Differential Revision: https://reviews.llvm.org/D91471
2020-11-14 04:56:56 -08:00
Paul C. Anagnostopoulos
f82f4bca37 [TableGen] Clean up more .td files
Differential Revision: https://reviews.llvm.org/D91431
2020-11-14 07:32:25 -05:00
Roman Lebedev
f948b65a66 Revert "clang-misexpect: Profile Guided Validation of Performance Annotations in LLVM"
See discussion in https://bugs.llvm.org/show_bug.cgi?id=45073 / https://reviews.llvm.org/D66324#2334485
the implementation is known-broken for certain inputs,
the bugreport was up for a significant amount of timer,
and there has been no activity to address it.
Therefore, just completely rip out all of misexpect handling.

I suspect, fixing it requires redesigning the internals of MD_misexpect.
Should anyone commit to fixing the implementation problem,
starting from clean slate may be better anyways.

This reverts commit 7bdad08429411e7d0ecd58cd696b1efe3cff309e,
and some of it's follow-ups, that don't stand on their own.
2020-11-14 13:12:38 +03:00
Craig Topper
207cb5cde4 [RISCV] Add test cases for fsrw/fslw that don't sign extend the result. NFC
These currently fail to select fsrw/fslw.
2020-11-13 23:31:16 -08:00
Arthur Eubanks
f99e276212 [test] Fix const-addr-no-neg-offset.ll under NPM 2020-11-13 23:29:58 -08:00
Mehdi Amini
5fd6b9a08c Revert "Switch libLLVMFrontendOpenACC to be a regular CMake library and not a "component""
This reverts commit e7ed27653292b2ec545e87204031282b4b237754.

Build is broken with  -DLLVM_LINK_LLVM_DYLIB=ON
2020-11-14 04:14:17 +00:00
Mehdi Amini
c98c27f79e Switch libLLVMFrontendOpenACC to be a regular CMake library and not a "component"
This library is only used in Flang at the moment and not tested withing LLVM.
Having it as a component is breaking llvm-config:

  $ bin/llvm-config --shared-mode
  llvm-config: error: component libraries and shared library

  llvm-config: error: missing: [...]/lib/libLLVMFrontendOpenACC.a

This will reverted when unit-tests are provided for it.

Reviewed By: clementval

Differential Revision: https://reviews.llvm.org/D91470
2020-11-14 02:18:25 +00:00