RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
Code Issues Projects Releases Wiki Activity
33,654 Commits 4 Branches 5 Tags 704 MiB
e3464e6bec
Commit Graph

150 Commits

Author SHA1 Message Date
Dan Gohman
e3464e6bec Change the x86 assembly output to use tab characters to separate the 
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
 2007-07-31 20:11:57 +00:00
Evan Cheng
3493ec0ce1 Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
llvm-svn: 40628
 2007-07-31 08:04:03 +00:00
Dan Gohman
0252aa07ee Re-apply 40504, but with a fix for the segfault it caused in oggenc: 
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555
 2007-07-27 17:16:43 +00:00
Evan Cheng
cb8f08ebca Reverting 40504 for now. It's breaking oggenc. 
llvm-svn: 40547
 2007-07-27 01:37:47 +00:00
Evan Cheng
7b20c11ccf Test case for PR1573. 
llvm-svn: 40539
 2007-07-26 17:45:57 +00:00
Evan Cheng
a681654ef4 Fix test. 
llvm-svn: 40536
 2007-07-26 17:07:03 +00:00
Dan Gohman
513dcba4f8 Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the 
x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504
 2007-07-26 00:31:09 +00:00
Dan Gohman
a2e07a38bc Use movaps to load a v4f32 build_vector of all-constant values into a 
register instead of loading each element individually.

llvm-svn: 40478
 2007-07-24 22:55:08 +00:00
Dan Gohman
df9edb66c2 Update these regression tests to accomodate X86InstrSSE.td now using movups/movaps 
for everything.

llvm-svn: 40101
 2007-07-20 16:31:26 +00:00
Evan Cheng
d846db5ab8 New test. 
llvm-svn: 40077
 2007-07-20 00:27:56 +00:00
Evan Cheng
d7a079b7e2 New test. 
llvm-svn: 40073
 2007-07-19 23:53:50 +00:00
Evan Cheng
b95db5ea4b Try fixing it again. 
llvm-svn: 40072
 2007-07-19 23:53:29 +00:00
Reid Spencer
44d34e9b61 For PR1553: 
Change the keywords for the zext and sext parameter attributes to be 
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.

llvm-svn: 40069
 2007-07-19 23:13:04 +00:00
Bill Wendling
649bfb8c03 Don't need the "&&" to glue lines together. 
llvm-svn: 40063
 2007-07-19 18:06:26 +00:00
Bill Wendling
ca081ee3f7 Testcase for PR1549 
llvm-svn: 40041
 2007-07-19 06:31:11 +00:00
Evan Cheng
626af8e187 New test. 
llvm-svn: 40020
 2007-07-18 21:39:16 +00:00
Dan Gohman
2fc9d5171e Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015
 2007-07-18 20:23:34 +00:00
Dan Gohman
4c140b7128 It's not necessary to do rounding for alloca operations when the requested 
alignment is equal to the stack alignment.

llvm-svn: 40004
 2007-07-18 16:29:46 +00:00
Evan Cheng
0c49836a9f Fix test. 
llvm-svn: 39976
 2007-07-17 18:16:09 +00:00
Evan Cheng
532b73311e Use push / pop for prologues and epilogues. 
llvm-svn: 39967
 2007-07-17 07:59:08 +00:00
Dale Johannesen
469ed8e17e Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816
 2007-07-13 17:13:54 +00:00
Evan Cheng
9f43f89d89 Add test case for PR1545. 
llvm-svn: 39749
 2007-07-11 19:29:05 +00:00
Dan Gohman
629311ca52 Change the peep for EXTRACT_VECTOR_ELT of BUILD_PAIR to look for 
the new CONCAT_VECTORS node type instead, as that's what legalize
uses now. And add a peep for EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT.

llvm-svn: 38503
 2007-07-10 18:20:44 +00:00
Dan Gohman
5202c50198 Add a regression test for folding spill code into scalar min and max. 
llvm-svn: 38492
 2007-07-10 15:34:29 +00:00
Chris Lattner
9ce649f66e force a cpu without SSE 
llvm-svn: 38466
 2007-07-09 17:35:18 +00:00
Chris Lattner
5f21d8c4a8 allow this to work on ppc-darwin 
llvm-svn: 38465
 2007-07-09 17:32:28 +00:00
Bill Wendling
3600c7a835 Allow a GR64 to be moved into an MMX register via the "movd" instruction. 
Still need to have JIT generate this code.

llvm-svn: 37863
 2007-07-04 00:19:54 +00:00
Dale Johannesen
a12e448c37 New testcases for rev 37847 (PR's 1489 and 1505). 
llvm-svn: 37848
 2007-07-03 00:58:37 +00:00
Dan Gohman
965e6efe24 Add a basic test-case for passing and returning <4 x double> and 
<8 x float> values on X86.

llvm-svn: 37845
 2007-07-02 16:23:47 +00:00
Dan Gohman
f46ec01deb New test case. DAGCombiner should be able to fold -sin(-x) 
in -enable-unsafe-fp-math mode.

llvm-svn: 37841
 2007-07-02 15:43:20 +00:00
Evan Cheng
bf3744d05b New test. 
llvm-svn: 37823
 2007-06-29 23:17:15 +00:00
Evan Cheng
f07b7f27f2 New test. 
llvm-svn: 37815
 2007-06-29 21:40:30 +00:00
John Criswell
57e5ed4b5a Convert .cvsignore files 
llvm-svn: 37801
 2007-06-29 16:35:07 +00:00
Evan Cheng
995493fd4a New tests. 
llvm-svn: 37787
 2007-06-29 00:27:18 +00:00
Evan Cheng
f1397aafd9 New test case: identity operation of RHS / LHS of a VECTOR_SHUFFLE. 
llvm-svn: 37637
 2007-06-19 00:06:08 +00:00
Chris Lattner
4534df9032 ensure we don't regress on these tests. We generate aweful code in x86-32 for 
these though.

llvm-svn: 37619
 2007-06-17 23:29:57 +00:00
Bill Wendling
ad8326e004 XFAILing until I can fix properly. 
llvm-svn: 37618
 2007-06-16 23:57:51 +00:00
Bill Wendling
e90b29f646 Testcase for MMX int to MMX register failure. 
llvm-svn: 37612
 2007-06-16 06:31:47 +00:00
Chris Lattner
f75572a776 make this test harder, include a tied register. 
llvm-svn: 37600
 2007-06-15 19:09:53 +00:00
Dale Johannesen
62f49dd524 Do not treat FP_REG_KILL as terminator in branch analysis (X86). 
llvm-svn: 37578
 2007-06-14 22:03:45 +00:00
Chris Lattner
ea380b16b7 new testcase for PR1495 
llvm-svn: 37452
 2007-06-06 01:21:46 +00:00
Evan Cheng
ba4c97df9f New test. 
llvm-svn: 37431
 2007-06-05 01:45:08 +00:00
Dale Johannesen
a68662e4a4 Tail merging wasn't working for predecessors of landing pads. PR 1496. 
llvm-svn: 37427
 2007-06-04 23:52:54 +00:00
Dale Johannesen
fd7f1ad2f7 Implement smarter algorithm for choosing which blocks to tail-merge. 
See test/CodeGen/X86/test-pic-jtbl.ll for a case where it works well;
shaves another 10K off our favorite benchmark.  I was hesitant about
this because of compile speed, but seems to do OK on a bootstrap.

llvm-svn: 37392
 2007-06-01 23:02:45 +00:00
Dale Johannesen
54db6d2e4d tail merging shrinks this code a bit. Could do more in future. 
llvm-svn: 37316
 2007-05-23 21:09:26 +00:00
Evan Cheng
cfb1ffc73f Add test for PR1259. 
llvm-svn: 37273
 2007-05-21 23:30:33 +00:00
Chris Lattner
ac4e2f1414 add source 
llvm-svn: 37253
 2007-05-19 01:22:52 +00:00
Chris Lattner
a0fc844390 new testcase 
llvm-svn: 37251
 2007-05-19 01:21:39 +00:00
Evan Cheng
c741fd8106 New test case. 
llvm-svn: 37174
 2007-05-17 18:49:50 +00:00
Chris Lattner
4922cfb5b2 testcase for PR1427 
llvm-svn: 37140
 2007-05-17 03:29:17 +00:00