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Commit Graph

215995 Commits

Author SHA1 Message Date
Roman Lebedev
e411ba6370 [NFCI][SimplifyCFG] simplifyCommonResume(): use DeleteDeadBlock() 2021-05-19 12:04:22 +03:00
Sergey Dmitriev
6d117dab29 [llvm-objcopy] Add support for '--' for delimiting options from input/output files
This will allow to use llvm-objcopy with file names that begin with dashes.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D102665
2021-05-19 01:56:46 -07:00
Fraser Cormack
5e139f014a [RISCV] Support INSERT_VECTOR_ELT into i1 vectors
Like the element extraction of these vectors, we choose to promote up to
an i8 vector type and perform the insertion there.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D102697
2021-05-19 09:41:50 +01:00
Roman Lebedev
1c68f789ee [NFCI] SimplifyCFGPass: mergeEmptyReturnBlocks(): use DeleteDeadBlocks()
In this case, it does the same thing as the original pattern does.

SimplifyCFG has a few lurking miscompilations about deleting blocks that
have their address taken, and consistently using DeleteDeadBlocks() instead
 of a hand-rolled pattern will allow to weed those cases out easierly.
2021-05-19 11:32:24 +03:00
Rong Xu
275da5fb80 Fix sanitizer test errors from commit 886629a8
Explictly handle the empty string in the Hash calculation.
2021-05-18 22:46:51 -07:00
Vitaly Buka
d474f1c2ce [libfuzzer] Update doc mentioning removed flags. 2021-05-18 22:40:42 -07:00
Arthur Eubanks
99f72113f5 [NewPM] Add options to PrintPassInstrumentation
To bring D99599's implementation in line with the existing
PrintPassInstrumentation, and to fix a FIXME, add more customizability
to PrintPassInstrumentation.

Introduce three new options. The first takes over the existing
"-debug-pass-manager-verbose" cl::opt.

The second and third option are specific to -fdebug-pass-structure. They
allow indentation, and also don't print analysis queries.

To avoid more golden file tests than necessary, prune down the
-fdebug-pass-structure tests.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D102196
2021-05-18 20:59:35 -07:00
Senran Zhang
9e6695ba98 [Utils][vim] Highlight CHECK-EMPTY: & CHECK-COUNT: directives
Reviewed By: porglezomp

Differential Revision: https://reviews.llvm.org/D101135
2021-05-18 23:42:23 -04:00
Joseph Huber
36d5499565 [Attributor] Change AAExecutionDomain to only accept intrinsics
Summary:
The OpenMP runtime functions don't always provide unique thread ID's to
determine if a basic block is truly single-threaded. Change the implementation
to only check NVPTX intrinsics for now.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D102700
2021-05-18 21:19:26 -04:00
Guozhi Wei
5f78ed293a [X86FixupLEAs] Transform the sequence LEA/SUB to SUB/SUB
This patch transforms the sequence

    lea (reg1, reg2), reg3
    sub reg3, reg4

to two sub instructions

    sub reg1, reg4
    sub reg2, reg4

Similar optimization can also be applied to LEA/ADD sequence.
The modifications to TwoAddressInstructionPass is to ensure the operands of ADD
instruction has expected order (the dest register of LEA should be src register
of ADD).

Differential Revision: https://reviews.llvm.org/D101970
2021-05-18 18:02:36 -07:00
Rong Xu
8bcc53c7a0 Fix a buildbot failure from commit 886629a8 2021-05-18 16:53:34 -07:00
LLVM GN Syncbot
7332433411 [gn build] Port 886629a8c9e5 2021-05-18 23:27:42 +00:00
Rong Xu
4e30d875bf [SampleFDO] New hierarchical discriminator for Flow Sensitive SampleFDO
This patch implements first part of Flow Sensitive SampleFDO (FSAFDO).
It has the following changes:
(1) disable current discriminator encoding scheme,
(2) new hierarchical discriminator for FSAFDO.

For this patch, option "-enable-fs-discriminator=true" turns on the new
functionality. Option "-enable-fs-discriminator=false" (the default)
keeps the current SampleFDO behavior. When the fs-discriminator is
enabled, we insert a flag variable, namely, llvm_fs_discriminator, to
the object. This symbol will checked by create_llvm_prof tool, and used
to generate a profile with FS-AFDO discriminators enabled. If this
happens, for an extbinary format profile, create_llvm_prof tool
will add a flag to profile summary section.

Differential Revision: https://reviews.llvm.org/D102246
2021-05-18 16:23:43 -07:00
Tomasz Miąsko
2eaabe6011 [Demangle][Rust] Speculative fix for bot build failure
> error: ‘InType’ is not a class, namespace, or enumeration
2021-05-19 00:40:24 +02:00
Alex Orlov
fb84758743 [symbolizer] Added StartAddress for the resolved function.
In many cases it is helpful to know at what address the resolved function starts.
This patch adds a new StartAddress member to the DILineInfo structure.

Reviewed By: jhenderson, dblaikie

Differential Revision: https://reviews.llvm.org/D102316
2021-05-19 02:38:13 +04:00
Fabian Sommer
877aa02c97 Default stack alignment of x86 NaCl to 16 bytes
X86 NaCl generally requires the stack to be aligned to 16 bytes.
This change was already implemented in two downstream NaCl compilers
based on llvm.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D102610
2021-05-18 15:16:59 -07:00
Tomasz Miąsko
1ed92ec621 [Demangle][Rust] Parse tuples
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102579
2021-05-19 00:04:42 +02:00
Tomasz Miąsko
b7d704310d [Demangle][Rust] Parse slice type
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102578
2021-05-19 00:04:41 +02:00
Tomasz Miąsko
52d80831c8 [Demangle][Rust] Parse array type
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102573
2021-05-19 00:04:41 +02:00
Tomasz Miąsko
e23e26628d [Demangle][Rust] Parse named types
Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102571
2021-05-19 00:04:41 +02:00
Sanjay Patel
62bb5f5167 [x86] add FMF propagation test for target-specific intrinsic; NFC 2021-05-18 17:45:40 -04:00
Sanjay Patel
2648c406c2 [x86] trim zeros from constants for readability; NFC 2021-05-18 17:45:40 -04:00
Arthur Eubanks
d51b2ca5b9 [docs] Fix broken docs after 1c7f32334 2021-05-18 14:38:12 -07:00
Arthur Eubanks
2682845f03 [NFC] Use ArgListEntry indirect types more in ISel lowering
For opaque pointers, we're trying to avoid uses of
PointerType::getElementType().

A couple of ISel places use PointerType::getElementType(). Some of these
are easy to fix by using ArgListEntry's indirect types.

The inalloca type wasn't stored there, as opposed to preallocated and
byval which have their indirect types available, so add it and use it.

This is a reland after an MSan fix in D102667.

Differential Revision: https://reviews.llvm.org/D101713
2021-05-18 14:30:22 -07:00
Arthur Eubanks
b8775b2a78 [TargetLowering] Only inspect attributes in the arguments for ArgListEntry
Parameter attributes are considered part of the function [1], and like
mismatched calling conventions [2], we can't have the verifier check for
mismatched parameter attributes.

This is a reland after fixing MSan issues in D102667.

[1] https://llvm.org/docs/LangRef.html#parameter-attributes
[2] https://llvm.org/docs/FAQ.html#why-does-instcombine-simplifycfg-turn-a-call-to-a-function-with-a-mismatched-calling-convention-into-unreachable-why-not-make-the-verifier-reject-it

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D101806
2021-05-18 14:30:22 -07:00
Arthur Eubanks
520e56b673 [MSan] Set zeroext on call arguments to msan functions with zeroext parameter attribute
ABI attributes need to match between the caller and callee.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D102667
2021-05-18 14:07:39 -07:00
Konstantin Zhuravlyov
17a1c72316 AMDGPU/Docs: Remove reserved MACH 0x3E (it is no longer reserved), sort MACHs by value 2021-05-18 16:57:56 -04:00
Neumann Hon
5bf2202796 [SystemZ] [z/OS] Add XPLINK64 Calling Convention to SystemZ
This patch adds the XPLINK64 calling convention to the SystemZ
backend. It specifies and implements the argument passing and
return value conventions.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D101010
2021-05-18 16:52:47 -04:00
Arthur Eubanks
7a1762f190 [NewPM] Don't mark AA analyses as preserved
Currently all AA analyses marked as preserved are stateless, not taking
into account their dependent analyses. So there's no need to mark them
as preserved, they won't be invalidated unless their analyses are.

SCEVAAResults was the one exception to this, it was treated like a
typical analysis result. Make it like the others and don't invalidate
unless SCEV is invalidated.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D102032
2021-05-18 13:49:03 -07:00
Mateusz Mikuła
fc1169936b [MinGW] Fix the cmake condition for -mbig-obj
This is a correction to D102419, fixing the condition to the
form that actually works as intended.
2021-05-18 23:48:15 +03:00
Arthur Eubanks
c9fe8a87e5 [OpaquePtr] Make loads and stores work with opaque pointers
Don't check that types match when the pointer operand is an opaque
pointer.

I would separate the Assembler and Verifier changes, but
verify-uselistorder in the Assembler test ends up running the verifier.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102450
2021-05-18 13:43:50 -07:00
Petr Hosek
fb817e8922 [CMake] Use -O0 for unittests under full LTO as well
We already use -O0 for unittests under ThinLTO, do the same for full LTO
where the compile time costs to runtime benefits tradeoff is even worse.

Differential Revision: https://reviews.llvm.org/D102718
2021-05-18 13:41:32 -07:00
Reid Kleckner
f168f78702 [PDB] Improve error handling when writes fail
Handle PDB writing errors like any other error in LLD: emit an error and
continue. This allows the linker to print timing data and summary data
after linking, which can be helpful for finding PDB size problems. Also
report how large the file would have been.

Example output:

lld-link: error: Output data is larger than 4 GiB. File size would have been 6,937,108,480
lld-link: error: failed to write PDB file ./chrome.dll.pdb
                                    Summary
--------------------------------------------------------------------------------
          33282 Input OBJ files (expanded from all cmd-line inputs)
              4 PDB type server dependencies
              0 Precomp OBJ dependencies
       33396931 Input type records
... snip ...
  Input File Reading:           59756 ms ( 45.5%)
  GC:                            7500 ms (  5.7%)
  ICF:                           3336 ms (  2.5%)
  Code Layout:                   6329 ms (  4.8%)
  PDB Emission (Cumulative):    46192 ms ( 35.2%)
    Add Objects:                27609 ms ( 21.0%)
      Type Merging:             16740 ms ( 12.8%)
      Symbol Merging:           10761 ms (  8.2%)
    Publics Stream Layout:       9383 ms (  7.1%)
    TPI Stream Layout:           1678 ms (  1.3%)
    Commit to Disk:              3461 ms (  2.6%)
--------------------------------------------------
Total Link Time:               131244 ms (100.0%)

Differential Revision: https://reviews.llvm.org/D102713
2021-05-18 13:17:17 -07:00
Simon Pilgrim
c2e072d615 [X86][AVX] createVariablePermute - correctly extend same-sized-vector indices (PR50356)
D101838 incorrectly handled indices vectors of the same size but with higher element counts to just bitcast to the target indices type instead of performing a ZERO_EXTEND_VECTOR_INREG
2021-05-18 20:30:46 +01:00
Sam Clegg
44e7ba66b7 [lld][WebAssembly] Enable string tail merging in debug sections
This is a followup to https://reviews.llvm.org/D97657 which
applied string tail merging to data segments.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48828

Differential Revision: https://reviews.llvm.org/D102436
2021-05-18 12:25:39 -07:00
Konstantin Zhuravlyov
73cf836d97 AMDGPU/NFC: Replace EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3E with EF_AMDGPU_MACH_AMDGCN_GFX1034
Differential Revision: https://reviews.llvm.org/D102708
2021-05-18 15:11:50 -04:00
Simon Pilgrim
cd7ead1b16 [X86][AVX] Add variable-permute test case from PR50356 2021-05-18 19:37:49 +01:00
Rafael Auler
69e63fa13a [RuntimeDyld] Add allowStubs/allowZeroSyms
This patch introduces functionality used by BOLT when
re-linking the final binary. It adds to MemoryManager a new member
function allowStubAllocation to control whether this MemoryManager
supports increasing code size with stubs or not. Since BOLT can
rewrite some files in-place, it needs to avoid stub insertion done
by the linker. This patch also introduces allowsZeroSymbols to the
JITSymbolResolver class, enabling us to finish a link successfully
even when some symbols resolve to the value zero. When rewriting a
binary, sometimes we do need to resolve a target to zero in case
the input binary calls address zero and we want to be bug
compatible. We also expose reassignSectionAddress as it is used by
BOLT.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D97898
2021-05-18 11:35:27 -07:00
Nikita Popov
ea8b19209c [LICM] Remove MaybePromotable set (PR50367)
The MaybePromotable set keeps track of loads/stores for which
promotion was not attempted yet. Normally, any load/stores that
are promoted in the current iteration will be removed from this
set, because they naturally MustAlias with the promoted value.
However, if the source program has UB with metadata claiming that
a store is NoAlias, while it is actually MustAlias, and multiple
different pointers are promoted in the same iteration, it can
happen that a store is removed that is still in the MaybePromotable
set, causing a use-after-free.

While this could be fixed by explicitly invalidating values in
MaybePromotable in the LoopPromoter, I'm going with the more
radical option of dropping the set entirely here and check all
load/stores on each promotion iteration. As promotion, and especially
repeated promotion, are quite rare, this doesn't seem to have any
impact on compile-time.

Fixes https://bugs.llvm.org/show_bug.cgi?id=50367.
2021-05-18 20:26:01 +02:00
Arthur Eubanks
91e23dda1f [NFC] Format PassesBindingsTests CMake like other unittests 2021-05-18 10:40:07 -07:00
Sanjay Patel
637d7aad14 [InstCombine] restrict funnel shift match to avoid miscompile
As noted in the post-commit discussion for:
https://reviews.llvm.org/rGabd7529625a73f405e40a63dcc446c41d51a219e

...that change exposed a logic hole that allows a miscompile
if the shift amount could exceed the narrow width:
https://alive2.llvm.org/ce/z/-i_CiM
https://alive2.llvm.org/ce/z/NaYz28

The restriction isn't necessary for a rotate (same operand for
both shifts), so we should adjust the matching for the shift
value as a follow-up enhancement:
https://alive2.llvm.org/ce/z/ahuuQb
2021-05-18 13:32:07 -04:00
Arthur Eubanks
ea15988f3a [test] Speculative fix for bots (round 2)
Bot has error "Failed to create target from default triple: Unable to
find target for this triple (no targets are registered)", likely because
we only initialized the native target, not the registered target if it's
different.

https://lab.llvm.org/buildbot/#/builders/86/builds/13664
2021-05-18 10:26:28 -07:00
Arthur Eubanks
58171eb768 [gn build] Rename PassesBindingsTests and add it to unittests 2021-05-18 10:26:00 -07:00
Sanjay Patel
6ddfe02013 [InstCombine] add tests for funnel shift miscompile; NFC 2021-05-18 13:18:39 -04:00
Arthur Eubanks
902d2930b3 Revert "[test] Speculative fix for bots"
This reverts commit 5c291482ec8bcd686044ebc0d4cffe7bf769521c.

unittests/Passes/CMakeFiles/PassesBindingsTests.dir/PassBuilderBindingsTest.cpp.o: In function `PassBuilderCTest::SetUp()':
PassBuilderBindingsTest.cpp:(.text._ZN16PassBuilderCTest5SetUpEv[_ZN16PassBuilderCTest5SetUpEv]+0x28): undefined reference to `LLVMInitializeARMTargetInfo'
2021-05-18 10:12:51 -07:00
Simon Pilgrim
db2db16d63 [X86] Use Skylake Server model for x86-64-v4 so we have full instruction coverage
The x86-64-v4 generic cpu arch supports AVX512BW/DQ/CD/VLX which isn't covered by the Haswell model, use the SkylakeServer model instead which is a lot closer to what the arch represents.

Differential Revision: https://reviews.llvm.org/D102553
2021-05-18 18:06:40 +01:00
Arthur Eubanks
3cf1e94194 [test] Speculative fix for bots
Bot has error "Failed to create target from default triple: Unable to
find target for this triple (no targets are registered)", likely because
we only initialized the native target, not the registered target if it's
different.

https://lab.llvm.org/buildbot/#/builders/86/builds/13664
2021-05-18 10:01:38 -07:00
Arthur Eubanks
4e7133736e [gn build] Add target for PassesBindingsTest 2021-05-18 10:01:19 -07:00
Jessica Paquette
d062dbe68c [AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
We can use an ORRWrs (mov) + SUBREG_TO_REG rather than a UBFX for G_ZEXT on
s32->s64.

This closer matches what SDAG does, and is likely more power efficient etc.

(Also fixed up arm64-rev.ll which had a fallback check line which was entirely
useless.)

Simple example: https://godbolt.org/z/h1jKKdx5c

Differential Revision: https://reviews.llvm.org/D102656
2021-05-18 10:00:00 -07:00
Roman Lebedev
05929e5791 [X86] AMD Zen 3: fix MULX modelling - don't forget about WriteIMulH (PR50387)
Otherwise lack thereof will be caught by a defensive check during
scheduling, and we'll crash.

I've literally never seen this syntax before..
2021-05-18 19:58:04 +03:00