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181232 Commits

Author SHA1 Message Date
Craig Topper
045bb331dd [X86] Add a DAG combine to replace vector loads feeding a v4i32->v2f64 CVTSI2FP/CVTUI2FP node with a vzload.
But only when the load isn't volatile.

This improves load folding during isel where we only have vzload
and scalar_to_vector+load patterns. We can't have full vector load
isel patterns for the same volatile load issue.

Also add some missing masked cvtsi2fp/cvtui2fp with vzload patterns.

llvm-svn: 364728
2019-07-01 07:09:31 +00:00
Craig Topper
20d2f0bfdb [X86] Add some additional load folding tests to vec_int_to_fp.ll/vec_int_to_fp-widen.ll and disable the peephole pass.
Also copy some missing test cases from vec_int_to_fp.ll to vec_int_to_fp-widen.ll

llvm-svn: 364727
2019-07-01 07:09:26 +00:00
Craig Topper
e0e2b4b23a [X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD.
We already had patterns that used scalar_to_vector+load. But we can
also have a vzload.

Found while investigating combining scalar_to_vector+load to vzload.

llvm-svn: 364726
2019-07-01 07:09:23 +00:00
Mike Spertus
226db54424 Clean up MSVC visualization of LLVM pointer types
Create separate natvis ptr and int views for PointerIntPair.
These are convenient in watch Windows and will be used by 
Clang visualizers to be checked in shortly

Also, removed deref views as the MSVC na format has
done the same thing natively since MSVC2013.

llvm-svn: 364723
2019-06-30 21:54:34 +00:00
Sanjay Patel
d0fe32bf62 [InstCombine] canonicalize fcmp+select to minnum/maxnum intrinsics
This is the opposite direction of D62158 (we have to choose 1 form or the other).
Now that we have FMF on the select, this becomes more palatable. And the benefits
of having a single IR instruction for this operation (less chances of missing folds
based on extra uses, etc) overcome my previous comments about the potential advantage
of larger pattern matching/analysis.

Differential Revision: https://reviews.llvm.org/D62414

llvm-svn: 364721
2019-06-30 13:40:31 +00:00
Fangrui Song
0d1da5593c Cleanup: llvm::bsearch -> llvm::partition_point after r364719
llvm-svn: 364720
2019-06-30 11:19:56 +00:00
Fangrui Song
9b1c36c2d7 [ADT] Implement llvm::bsearch() with std::partition_point()
Summary:
Delete the begin-end form because the standard std::partition_point
can be easily used as a replacement.

The ranges-style llvm::bsearch will be renamed to llvm::partition_point
in the next clean-up patch.

The name "bsearch" doesn't meet people's expectation because in C:

> If two or more members compare equal, which member is returned is unspecified.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D63718

llvm-svn: 364719
2019-06-30 09:17:59 +00:00
Craig Topper
ff0bc8f8ac [X86] Custom lower AVX masked loads to masked load and vselect instead of selecting a maskmov+vblend during isel.
AVX masked loads only support 0 as the value for masked off elements.
So we need an extra blend to support other values. Previously we
expanded the masked load to two instructions with isel patterns.
With this patch we now insert the vselect during lowering and it
will be separately selected as a blend.

llvm-svn: 364718
2019-06-30 06:46:37 +00:00
Craig Topper
6357298c13 [SelectionDAG] Use the memory VT instead of result VT for FoldingSet profiling in getMaskedLoad/getMaskedStore.
This matches what is done by the Profile function. Otherwise CSE
won't work properly.

llvm-svn: 364717
2019-06-30 06:46:33 +00:00
Nikita Popov
3583d560a1 [LFTR] Rephrase getLoopTest into "based-on" check; NFCI
What we want to know here is whether we're already using this value
for the loop condition, so make the query about that. We can extend
this to a more general "based-on" relationship, rather than a direct
icmp use later.

llvm-svn: 364715
2019-06-29 15:12:59 +00:00
Sanjay Patel
8026b84389 [InstCombine] canonicalize fmin/fmax to LLVM intrinsics minnum/maxnum
This transform came up in D62414, but we should deal with it first.
We have LLVM intrinsics that correspond exactly to libm calls (unlike
most libm calls, these libm calls never set errno).
This holds without any fast-math-flags, so we should always canonicalize
to those intrinsics directly for better optimization.
Currently, we convert to fcmp+select only when we have FMF (nnan) because
fcmp+select does not preserve the semantics of the call in the general case.

Differential Revision: https://reviews.llvm.org/D63214

llvm-svn: 364714
2019-06-29 14:28:54 +00:00
Nikita Popov
e4294b54e2 [LFTR] Remove unnecessary latch check; NFCI
The whole indvars pass works on loops in simplified form, so there
is always a unique latch. Convert the condition into an assertion
in needsLFTR (though we also assert this in later LFTR functions).

Additionally update the comment on getLoopTest() now that we are
dealing with multiple exits.

llvm-svn: 364713
2019-06-29 12:41:02 +00:00
Roman Lebedev
4e8fdbd5d8 [InstCombine] Shift amount reassociation (PR42391)
Summary:
Given pattern:
`(x shiftopcode Q) shiftopcode K`
we should rewrite it as
`x shiftopcode (Q+K)`  iff `(Q+K) u< bitwidth(x)`
This is valid for any shift, but they must be identical.

* https://rise4fun.com/Alive/9E2
* exact on both lshr => exact https://rise4fun.com/Alive/plHk
* exact on both ashr => exact https://rise4fun.com/Alive/QDAA
* nuw on both shl => nuw https://rise4fun.com/Alive/5Uk
* nsw on both shl => nsw https://rise4fun.com/Alive/0plg

Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42391 | PR42391]].

Reviewers: spatel, nikic, RKSimon

Reviewed By: nikic

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63812

llvm-svn: 364712
2019-06-29 11:51:50 +00:00
Roman Lebedev
6ff8b94a9a [IR][Patternmatch] Add m_SpecificInt_ULT() predicate
Summary:
Match an integer or vector with every element unsigned less than the
Threshold. For vectors, this includes constants with undefined elements.

FIXME: is it worth generalizing this to simply take ICmpInst::Predicate?

Reviewers: craig.topper, spatel, nikic

Reviewed By: spatel

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63811

llvm-svn: 364711
2019-06-29 11:51:37 +00:00
Dmitry Venikov
90bf1784c8 [APInt] Fix getBitsNeeded for INT_MIN values
Summary: This patch fixes behaviour of APInt::getBitsNeeded for INT_MIN 10 bits values.

Reviewers: regehr, RKSimon

Reviewed By: RKSimon

Subscribers: grandinj, dexonsmith, kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63691

llvm-svn: 364710
2019-06-29 11:38:12 +00:00
Nikita Popov
82bf7cc229 [LFTR] Fix post-inc pointer IV with truncated exit count (PR41998)
Fixes https://bugs.llvm.org/show_bug.cgi?id=41998. Usually when we
have a truncated exit count we'll truncate the IV when comparing
against the limit, in which case exit count overflow in post-inc
form doesn't matter. However, for pointer IVs we don't do that, so
we have to be careful about incrementing the IV in the wide type.

I'm fixing this by removing the IVCount variable (which was
ExitCount or ExitCount+1) and replacing it with a UsePostInc flag,
and then moving the actual limit adjustment to the individual cases
(which are: pointer IV where we add to the wide type, integer IV
where we add to the narrow type, and constant integer IV where we
add to the wide type).

Differential Revision: https://reviews.llvm.org/D63686

llvm-svn: 364709
2019-06-29 09:24:12 +00:00
Sam Clegg
a5a2205776 Partial revert of "[llvm-ar] Document response file support in --help"
This is partial revert of 70a8027c60fe1f95e8a8a1ff6575ebf8778d3544.

The test apparently failed on win32 bots due to the way slashes in
pathnames are handled.

llvm-svn: 364705
2019-06-29 01:53:26 +00:00
Matt Arsenault
d13ac7e93c AMDGPU/GlobalISel: Add some more tests for icmp select
llvm-svn: 364703
2019-06-29 00:55:16 +00:00
Matt Arsenault
9eb156737f AMDGPU/GlobalISel: RegBankSelect for update.dpp
llvm-svn: 364701
2019-06-29 00:44:36 +00:00
Matt Arsenault
5dd3fb80c4 AMDGPU/GlobalISel: RegBankSelect for atomic.inc/atomic.dec
llvm-svn: 364699
2019-06-29 00:39:20 +00:00
Matt Arsenault
75e02974f3 AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
llvm-svn: 364698
2019-06-29 00:33:13 +00:00
Matt Arsenault
a229c10e69 AMDGPU/GlobalISel: RegBankSelect for some easy intrinsics
llvm-svn: 364697
2019-06-29 00:29:56 +00:00
Matt Arsenault
f2f3b70381 AMDGPU/GlobalISel: RegBankSelect for icmp/fcmp intrinsics
llvm-svn: 364696
2019-06-29 00:28:52 +00:00
Matt Arsenault
6c3d7544cc AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.fmas
llvm-svn: 364695
2019-06-29 00:25:53 +00:00
Matt Arsenault
30df001b5d AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
llvm-svn: 364694
2019-06-29 00:22:28 +00:00
Philip Reames
4e43cc3a25 [IndVars] Remove a bit of manual constant folding [NFC]
SCEV is more than capable of folding (add x, trunc(0)) to x.  

llvm-svn: 364693
2019-06-29 00:19:31 +00:00
Matt Arsenault
25324b5081 AMDGPU: Add baseline test for packed shufflevector
llvm-svn: 364691
2019-06-28 23:43:40 +00:00
Wouter van Oortmerssen
1ff5ed90df [WebAssembly] Assembler: support .int16/32/64 directives.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63959

llvm-svn: 364689
2019-06-28 22:20:33 +00:00
Wouter van Oortmerssen
cc716d78a8 [WebAssembly] Allow @object in .type directives.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63955

llvm-svn: 364688
2019-06-28 21:53:11 +00:00
Sanjay Patel
3620c94af7 [x86] remove stale comment about cmov; NFC
The cmov node used to sometimes return a glue result (and that's what
'flag' meant in this context), but that was removed with D38664.

llvm-svn: 364687
2019-06-28 21:45:55 +00:00
Cameron McInally
e7a7f50943 [NFC][NewGVN] Explicitly check fpmath metadata in fpmath.ll
Suggested in D63933.

llvm-svn: 364685
2019-06-28 21:39:08 +00:00
Sanjay Patel
a04e50b4eb [Lanai] auto-generate complete test checks; NFC
This file will fail with a common codegen transform that
I'm looking at, and I can't tell if that's an improvement
or regression based on the sparse checking.

llvm-svn: 364684
2019-06-28 20:45:32 +00:00
Wouter van Oortmerssen
d3dc642675 [WebAssembly] Assembler: Allow offsets and p2align in symbol load.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63951

llvm-svn: 364682
2019-06-28 20:31:13 +00:00
Wouter van Oortmerssen
34f2e2f14b [WebAssembly] Assembler: Improve section parsing.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63947

llvm-svn: 364681
2019-06-28 20:29:16 +00:00
Cameron McInally
aa9574f6e6 [NewGVN] Add unary FNeg support to NewGVN pass
Differential Revision: https://reviews.llvm.org/D63933

llvm-svn: 364680
2019-06-28 20:09:32 +00:00
Cameron McInally
f51987bd8e [GVNSink] Add unary FNeg support to GVNSink pass
Differential Revision: https://reviews.llvm.org/D63900

llvm-svn: 364678
2019-06-28 19:57:31 +00:00
Erik Pilkington
e48e888008 [demangle] Support for C++2a char8_t
llvm-svn: 364677
2019-06-28 19:54:19 +00:00
Brad Smith
1137ec78d2 Default to Secure PLT on PPC for musl libc.
This matches the default settings of clang.

llvm-svn: 364675
2019-06-28 19:48:31 +00:00
Sam Clegg
b388897043 [llvm-ar] Document response file support in --help
Also a test for this.

Differential Revision: https://reviews.llvm.org/D63836

llvm-svn: 364673
2019-06-28 18:48:05 +00:00
Lang Hames
4890f2a545 Re-apply r364600 with fixes.
Fix: MachO/X86_64_RELOC_GOT is a 32-bit reloc, so only compare 32 bits.
llvm-svn: 364672
2019-06-28 18:36:59 +00:00
Rainer Orth
20567f8219 [unittests][Support] Fix LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions on Solaris
LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions currently
FAILs on Solaris:

  FAIL: LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions (2940 of 51555)
  ******************** TEST 'LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions' FAILED ********************
  Note: Google Test filter = FileSystemTest.permissions
  [==========] Running 1 test from 1 test case.
  [----------] Global test environment set-up.
  [----------] 1 test from FileSystemTest
  [ RUN      ] FileSystemTest.permissions
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1705: Failure
  Value of: CheckPermissions(fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1712: Failure
  Value of: CheckPermissions(fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1719: Failure
  Value of: CheckPermissions(fs::all_read | fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1722: Failure
  Value of: CheckPermissions(fs::all_perms)
    Actual: false
  Expected: true
  [  FAILED  ] FileSystemTest.permissions (0 ms)
  [----------] 1 test from FileSystemTest (0 ms total)
  
  [----------] Global test environment tear-down
  [==========] 1 test from 1 test case ran. (1 ms total)
  [  PASSED  ] 0 tests.
  [  FAILED  ] 1 test, listed below:
  [  FAILED  ] FileSystemTest.permissions
  
   1 FAILED TEST

Checking with truss reveals that this is the same issue as on AIX and
documented in chmod(2):

  If the process is not a privileged process and the file is not a direc-
  tory, mode bit 01000 (S_ISVTX, the sticky bit) is cleared.

The following patch fixes this in the same way.  Tested on amd64-pc-solaris2.11.

Differential Revision: https://reviews.llvm.org/D63598

llvm-svn: 364671
2019-06-28 18:29:18 +00:00
Jinsong Ji
d8b5b763b2 [UpdateChecks] Add support for armv7-apple-darwin
armv7-apple-darwin was not supported well, the script can't generate
checks.

https://reviews.llvm.org/D60601/new/#inline-568671

Differential Revision: https://reviews.llvm.org/D63939

llvm-svn: 364668
2019-06-28 18:07:19 +00:00
Simon Pilgrim
b52c8f5066 [X86] CombineShuffleWithExtract - recurse through EXTRACT_SUBVECTOR chain
llvm-svn: 364667
2019-06-28 17:57:32 +00:00
Peter Collingbourne
ac22a944f7 hwasan: Remove the old frame descriptor mechanism.
Differential Revision: https://reviews.llvm.org/D63470

llvm-svn: 364665
2019-06-28 17:53:26 +00:00
Roman Lebedev
e751570ab5 [NFC][Codegen] Revisit test coverage for X % C == 0 fold once more (add tests with '1' divisor)
llvm-svn: 364661
2019-06-28 17:26:28 +00:00
Wouter van Oortmerssen
4f70d23e34 [WebAssembly] Added visibility and ident directives to WasmAsmParser.
Summary:
These are output by clang -S, so can now be roundtripped thru clang.

(partially) fixes: https://bugs.llvm.org/show_bug.cgi?id=34544

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63901

llvm-svn: 364658
2019-06-28 16:51:06 +00:00
Roman Lebedev
5e1e493a46 [NFC][InstCombine] Shift amount reassociation: revisit flag preservation tests
llvm-svn: 364657
2019-06-28 16:36:53 +00:00
Dmitry Preobrazhensky
6c92b88d5f [AMDGPU][MC] Fix 2 for sanitizer failure in 364645
llvm-svn: 364656
2019-06-28 16:28:46 +00:00
Sam Tebbs
9cb186cbd7 [ARM] Add support for the MVE long shift instructions
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.

The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.

test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.

Differential Revision: https://reviews.llvm.org/D63430

llvm-svn: 364654
2019-06-28 15:43:31 +00:00
Max Moroz
33e65f7a8d [llvm-cov[ Fix lcov coverage report contains functions from other compilation units.
Summary: Patch by Chuan Qiu (@eagleonhill).

Reviewers: Dor1s

Reviewed By: Dor1s

Subscribers: lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63571

llvm-svn: 364653
2019-06-28 15:38:25 +00:00