1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
Commit Graph

132277 Commits

Author SHA1 Message Date
Simon Pilgrim
b617a8ce13 [X86][AVX] Regenerated avx upgraded intrinsics tests
llvm-svn: 270422
2016-05-23 12:39:06 +00:00
Diana Picus
0a143f0f02 [BPF] Remove exit-on-error flag in test (PR27766)
The exit-on-error flag on the many_args1.ll test is needed to avoid an
unreachable in BPFTargetLowering::LowerCall. We can also avoid it by ignoring
any superfluous arguments to the call (i.e. any arguments after the first 5).

Fixes PR27766

llvm-svn: 270419
2016-05-23 12:33:34 +00:00
Chris Dewhurst
14488dfcf0 [Sparc] LEON erratum fix - Delay Slot Filler modification.
This code should have been with the previous check-in (r270417) and prevents the DelaySlotFiller pass being utilized in functions where the erratum fix has been applied as this will break the run-time code.

llvm-svn: 270418
2016-05-23 11:52:28 +00:00
Chris Dewhurst
11fab31200 [Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction.
Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix.

The code will have no effect for other Sparc, but non-LEON processors.

Differential Review: http://reviews.llvm.org/D20353

llvm-svn: 270417
2016-05-23 10:56:36 +00:00
Sam Kolton
59aa17c27c [AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms.
Reviewers: nhaustov, tstellarAMD

Subscribers: kzhuravl, arsenm

Differential Revision: http://reviews.llvm.org/D20166

llvm-svn: 270415
2016-05-23 09:59:02 +00:00
Jacob Baungard Hansen
1036b51c05 Test commit
llvm-svn: 270414
2016-05-23 09:41:44 +00:00
Davide Italiano
d227f1d8ce [SCCP] Update comment to reflect reality.
llvm-svn: 270413
2016-05-23 09:34:50 +00:00
Richard Smith
c9eabc5991 Enable use of sigaltstack for signal handlers when available. With this,
backtraces from the signal handler on stack overflow now work reliably (on my
system at least...).

llvm-svn: 270395
2016-05-23 06:47:37 +00:00
Craig Topper
62ac946928 [X86] Use instruction aliases to replace custom asm parser code for optimizing moves to use 2 byte VEX prefix.
llvm-svn: 270394
2016-05-23 04:02:27 +00:00
David Majnemer
39c1ab7efb Revert "Modify emitTypeInformation to use MemoryTypeTableBuilder"
This reverts commit r270106.  It results in certain function types
omitted in the output.

llvm-svn: 270389
2016-05-23 01:37:45 +00:00
Craig Topper
ae0615175a [AVX512] Add patterns to implement stores of extracts of least signficant subvectors using XMM or YMM stores instead of the vector extract instructions.
Similar is already done for AVX and we had lost it going to AVX512VL.

llvm-svn: 270383
2016-05-22 23:44:33 +00:00
Lang Hames
c2f93ebd16 [Kaleidoscope] Fix static global ordering to prevent crash on exit.
If TheModule is declared before LLVMContext then it will be destructed after it,
crashing when it tries to deregister itself from the destructed context.

llvm-svn: 270381
2016-05-22 22:48:36 +00:00
Simon Pilgrim
6d1bf65d77 [X86][SSE] Added extra i8 extract element test
llvm-svn: 270379
2016-05-22 20:35:42 +00:00
Sanjay Patel
b2763427c2 [x86, AVX] don't add a vzeroupper if that's what the code is already doing (PR27823)
This isn't the complete fix, but it handles the trivial examples of duplicate vzero* ops in PR27823:
https://llvm.org/bugs/show_bug.cgi?id=27823
...and amusingly, the bogus cases already exist as regression tests, so let's take this baby step.

We'll need to do more in the general case where there's legitimate AVX usage in the function + there's
already a vzero in the code.

Differential Revision: http://reviews.llvm.org/D20477

llvm-svn: 270378
2016-05-22 20:22:47 +00:00
Sanjay Patel
e49c68f164 [x86, AVX] add test file to show vzeroupper pass excesses
llvm-svn: 270375
2016-05-22 19:55:48 +00:00
Sanjay Patel
305c2f05c5 reduce indent; NFC
llvm-svn: 270372
2016-05-22 17:08:52 +00:00
Sanjay Patel
80f08c1c8b use 'auto' with 'dyn_cast'; fix formatting; NFC
llvm-svn: 270370
2016-05-22 16:07:20 +00:00
Sanjay Patel
be15a9a346 [ValueTracking, InstCombine] extend isKnownToBeAPowerOfTwo() to handle vector splat constants
We could try harder to handle non-splat vector constants too, 
but that seems much rarer to me.

Note that the div test isn't resolved because there's a check
for isIntegerTy() guarding that transform.

Differential Revision: http://reviews.llvm.org/D20497

llvm-svn: 270369
2016-05-22 15:41:53 +00:00
Igor Breger
7450d33b3c [AVX512] Implement missing patterns for any_extend load lowering.
Differential Revision: http://reviews.llvm.org/D20513

llvm-svn: 270357
2016-05-22 10:21:04 +00:00
Craig Topper
40ab0cb8bb [AVX512] The AVX512 file only need subtract_subvector index 0 patterns where the source is 512-bits. The 256-bit source patterns were redundant with AVX.
llvm-svn: 270356
2016-05-22 07:40:58 +00:00
Craig Topper
ec1c660b77 [AVX512] Add an AddedComplexity line to the 512-bit insert_subvector undef index 0 patterns. This gives them higher priority than the memory patterns. This matches AVX1/2.
llvm-svn: 270355
2016-05-22 07:40:40 +00:00
Craig Topper
b6b424b279 [AVX512] Change the AddedComplexity on some patterns to match their AVX/SSE equivalents. This helps group them close together in the isel tables and enable table compression.
llvm-svn: 270354
2016-05-22 06:09:34 +00:00
Xinliang David Li
b77f901eb5 bug fix: trim section specifier name length
llvm-svn: 270349
2016-05-22 01:21:21 +00:00
Craig Topper
b3773ac60d [X86] Add a common check-prefix to both run lines on a test so identical checks appear just once.
llvm-svn: 270345
2016-05-22 00:39:33 +00:00
Craig Topper
a6980162a3 [AVX512] Add a couple patterns to fix some cases where two vector mask inversions could appear in a row.
llvm-svn: 270344
2016-05-22 00:39:30 +00:00
Craig Topper
0754f22fa5 [AVX512] Remove seemingly unnecessary AddedComplexity adjustment.
llvm-svn: 270343
2016-05-22 00:39:27 +00:00
Xinliang David Li
38f87668c3 [profile] Static counter allocation for value profiling (part-1)
Differential Revision: http://reviews.llvm.org/D20459

llvm-svn: 270336
2016-05-21 22:55:34 +00:00
Craig Topper
c1c9bee262 [X86] Remove unnecessary alignment check on patterns that use VEXTRACTF128 for integer types when only AVX1 is supported.
llvm-svn: 270335
2016-05-21 22:50:18 +00:00
Craig Topper
ff8ed4829f [AVX512] Add patterns for extracting subvectors and storing to memory.
llvm-svn: 270334
2016-05-21 22:50:14 +00:00
Craig Topper
e6ae74c913 [AVX512] Capitalize the Z in VEXTRACTPSzmr. Lowercase z has been primarily used to indicating the zero masking behavior which is not the case here. NFC
llvm-svn: 270333
2016-05-21 22:50:11 +00:00
Craig Topper
29ae9d7e02 [AVX512] Rename vector extract instructions so 'mr' intead of 'rm' to reflect the fact that memory is the destination.
llvm-svn: 270332
2016-05-21 22:50:09 +00:00
Craig Topper
6bf6b5c2f4 [AVX512] Fix copy/paste mistake a I made in a comment.
llvm-svn: 270331
2016-05-21 22:50:04 +00:00
Chad Rosier
d150a4d1c1 Fix 80-column violation.
llvm-svn: 270329
2016-05-21 21:12:06 +00:00
Hal Finkel
be81a6f808 [LiveIntervalAnalysis] Don't dereference an end iterator in repairIntervalsInRange
This fixes a bug introduced in:

  r262115 - CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC

The iterator End here might == MBB->end(), and so we can't unconditionally
dereference it. This often goes unnoticed (I don't have a test case that always
crashes, and ASAN does not catch it either) because the function call arguments are
turned right back into iterators. MachineInstrBundleIterator's constructor,
however, does have an assert which might randomly fire.

llvm-svn: 270323
2016-05-21 16:03:50 +00:00
Michael Zuckerman
306643b672 [Clang][AVX512][intrinsics] Fix rcp and sqrt intrinsics.
Differential Revision: http://reviews.llvm.org/D20438

llvm-svn: 270322
2016-05-21 14:44:18 +00:00
Michael Zuckerman
3d906b3ef7 [Clang][AVX512][intrinsics] Fix vscalef intrinsics.
Differential Revision: http://reviews.llvm.org/D20324

llvm-svn: 270321
2016-05-21 11:09:53 +00:00
George Rimar
8a63746f19 [llvm-readobj] - Teach readobj to recognize SHF_COMPRESSED flag.
Main problem here was that SHF_COMPRESSED has the same value with
XCORE_SHF_CP_SECTION, which was included as standart (common) flag.
As far I understand xCore is a family of controllers and it that
means it's constant should be processed separately,
only if e_machine == EM_XCORE, otherwise llvm-readobj would output
different constants twice for compressed section:

Flags [
..
SHF_COMPRESSED (0x800)
..
XCORE_SHF_CP_SECTION (0x800)
..
]

what probably does not make sence if you're not working with xcore file.

Differential revision: http://reviews.llvm.org/D20273

llvm-svn: 270320
2016-05-21 10:16:58 +00:00
Craig Topper
79cd5a6b41 [AVX512] Add patterns for VEXTRACT v16i16->v8i16 and v32i8->v16i8. Disable AVX2 versions of vector extract when AVX512VL is enabled.
llvm-svn: 270318
2016-05-21 07:08:56 +00:00
Craig Topper
f3e023e70e [AVX512] Disable AVX2 VPERMD, VPERMQ, VPERMPS, and VPERMPD patterns when AVX512VL is enabled. Also add shuffle comment printing for AVX512VL VPERMPD/VPERMQ to keep some tests that now use these instructions instead of the AVX2 ones.
llvm-svn: 270317
2016-05-21 06:07:18 +00:00
Craig Topper
30a8fe51db [AVX512] Disable AVX/AVX2 VBROADCASTSS/VBROADCASTSD patterns when AVX512VL is enabled.
llvm-svn: 270316
2016-05-21 05:47:25 +00:00
Craig Topper
12c223c367 [AVX512] Use update_llc_test_checks to update some tests so we can see all the instruction encodings and ensure everything is with EVEX.
llvm-svn: 270315
2016-05-21 05:46:58 +00:00
David Majnemer
cb9616636d [SimplifyCFG] Remove cleanuppads which are empty except for calls to lifetime.end
A cleanuppad is not cheap, they turn into many instructions and result
in additional spills and fills.  It is not worth keeping a cleanuppad
around if all it does is hold a lifetime.end instruction.

N.B.  We first try to merge the cleanuppad with another cleanuppad to
avoid dropping the lifetime and debug info markers.

llvm-svn: 270314
2016-05-21 05:12:32 +00:00
Craig Topper
e4f5166f4f [AVX512] Fix test cases I missed in r270311.
llvm-svn: 270313
2016-05-21 03:59:55 +00:00
Matt Arsenault
c4ee204f5c AMDGPU: Define priorities for register classes
Allocating larger register classes first should give better allocation
results (and more importantly for myself, make the lit tests more stable
with respect to scheduler changes).

Patch by Matthias Braun

llvm-svn: 270312
2016-05-21 03:55:07 +00:00
Craig Topper
2b54c30436 [AVX512] Disable AVX/AVX2 patterns for VPSADBW and VPMULUDQ when the AVX512VL/AVX512BWI equivalents are available.
llvm-svn: 270311
2016-05-21 03:52:32 +00:00
Craig Topper
8ca6c23ba5 [X86] Convert some SSE2/AVX2 intrinsics to ISD opcodes during lowering instead of pattern matching the intrinsics. This unifies handling with AVX512 and allows these intrinsics to select EVEX encoded instructions to increase available registers.
llvm-svn: 270310
2016-05-21 03:52:28 +00:00
Sanjoy Das
472411c719 [IRCE] Don't use an allocator for range checks; NFC
The InductiveRangeCheck struct is only five words long; so passing these
around value is fine.  The allocator makes the code look more complex
than it is.

llvm-svn: 270309
2016-05-21 02:52:13 +00:00
Sanjoy Das
2e4b716313 [IRCE] Don't pass IRBuilder<> where unnecessary; NFC
llvm-svn: 270308
2016-05-21 02:31:51 +00:00
Matt Arsenault
1eaf7c8b10 AMDGPU: Cleanup lowering actions
These are kind of a mess and hard to follow, particularly
for loads and stores. Fix various redundant, unnecessary
and dead settings.

llvm-svn: 270307
2016-05-21 02:27:49 +00:00
Sanjoy Das
9b7c91f0ad [GuardWidening] Fix incorrect use of remove_if
I had used `std::remove_if` under the assumption that it moves the
predicate matching elements to the end, but actaully the elements
remaining towards the end (after the iterator returned by
`std::remove_if`) are indeterminate.  Fix the bug (and make the code
more straightforward) by using a temporary SmallVector, and add a test
case demonstrating the issue.

llvm-svn: 270306
2016-05-21 02:24:44 +00:00