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Commit Graph

138398 Commits

Author SHA1 Message Date
George Rimar
e4c65e9b9b Revert r282235 "[llvm-dwarfdump] - Teach dwarfdump to dump gdb-index section."
It broke BB:
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/15856

llvm-svn: 282238
2016-09-23 10:12:56 +00:00
Alexey Bataev
5e200a4d72 [InstCombine] Fix for PR29124: reduce insertelements to shufflevector
If inserting more than one constant into a vector:

define <4 x float> @foo(<4 x float> %x) {
  %ins1 = insertelement <4 x float> %x, float 1.0, i32 1
  %ins2 = insertelement <4 x float> %ins1, float 2.0, i32 2
  ret <4 x float> %ins2
}

InstCombine could reduce that to a shufflevector:

define <4 x float> @goo(<4 x float> %x) {
 %shuf = shufflevector <4 x float> %x, <4 x float> <float undef, float 1.0, float 2.0, float undef>, <4 x i32><i32 0, i32 5, i32 6, i32 3>
 ret <4 x float> %shuf
}
Also, InstCombine tries to convert shuffle instruction to single insertelement, if one of the vectors is a constant vector and only a single element from this constant should be used in shuffle, i.e.
shufflevector <4 x float> %v, <4 x float> <float undef, float 1.0, float
undef, float undef>, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> ->
insertelement <4 x float> %v, float 1.0, 1

Differential Revision: https://reviews.llvm.org/D24182

llvm-svn: 282237
2016-09-23 09:14:08 +00:00
George Rimar
7dd3eaf20c [llvm-dwarfdump] - Teach dwarfdump to dump gdb-index section.
gold linker's --gdb-index option currently is able to create the .gdb_index section that allows GDB to locate and read the .dwo files as it needs them,
this helps reduce the total size of the object files processed by the linker.

More info about that:
https://gcc.gnu.org/wiki/DebugFission
https://sourceware.org/gdb/onlinedocs/gdb/Index-Section-Format.html

Patch teaches dwarfdump tool to dump this section.

Differential revision: https://reviews.llvm.org/D21503

llvm-svn: 282235
2016-09-23 09:09:26 +00:00
Valery Pykhtin
8bae56ae1d [AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
Differential revision: https://reviews.llvm.org/D24738

llvm-svn: 282234
2016-09-23 09:08:07 +00:00
Craig Topper
8e59adb433 [AVX-512] Split X86ISD::VFPROUND and X86ISD::VFPEXT into separate opcodes for each type constraint.
This revealed that scalar intrinsics could create nodes with a rounding mode of FROUND_CUR_DIRECTION, but the patterns didn't check for it. It just worked because isel doesn't check operand count and we had a pattern without the rounding mode argument at all.

llvm-svn: 282231
2016-09-23 06:24:43 +00:00
Craig Topper
0358026c76 [AVX-512] Add separate ISD opcodes for each form of CVT instructions. Don't reuse non-X86 ISD opcodes with extra X86 specific arguments.
llvm-svn: 282230
2016-09-23 06:24:39 +00:00
Craig Topper
f8270c27ed [AVX-512] Use different ISD opcodes for some of the scalar intrinsic lowering. Isel is not very robust against using the same ISD opcode with different number of operands so its better to separate.
llvm-svn: 282229
2016-09-23 06:24:35 +00:00
Kostya Serebryany
cc6b86b16e [libFuzzer] be more precise about what we reset in TracePC
llvm-svn: 282225
2016-09-23 02:18:59 +00:00
Kostya Serebryany
763d4bc96b [libFuzzer] fix merging with trace-pc-guard
llvm-svn: 282224
2016-09-23 01:58:51 +00:00
Tom Stellard
a377ff1511 AMDGPU/SI: Include implicit arguments in kernarg_segment_byte_size
Reviewers: arsenm

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D24835

llvm-svn: 282223
2016-09-23 01:33:26 +00:00
Kostya Serebryany
5cd1f5a82d [libFuzzer] simplify the TracePC logic
llvm-svn: 282222
2016-09-23 01:20:07 +00:00
Quentin Colombet
052c0b8e6a [RegisterBankInfo] Mark the dump methods with LLVM_DUMP_METHOD.
NFC

llvm-svn: 282221
2016-09-23 00:59:12 +00:00
Quentin Colombet
ad7834b866 [AArch64][RegisterBankInfo] Sanity check TableGen'ed like inputs.
Make sure the entries written to mimic the behavior of TableGen are
sane.

llvm-svn: 282220
2016-09-23 00:59:07 +00:00
Kostya Serebryany
1f0aefdb84 [libFuzzer] move value profiling logic into TracePC
llvm-svn: 282219
2016-09-23 00:46:18 +00:00
Tom Stellard
a0456d6c9f Triple: Add opencl environment type
Summary:
For AMDGPU, we have been using the operating system component of the triple
for specifying the low-level runtime that is being used.  The rationale for
this is that the host operating system (e.g. Linux) is irrelevant for GPU code,
since its execution enviroment will be mostly controled by the low-level runtime
being used to execute the code.

In most cases, higher level languages have their own runtime which is
implemented on top of the low-level runtime.  The kernel ABIs of each
language mostly depend on the low-level runtime, but there may be some
slight differences between languages.  OpenCL for example, may append
additional arguments to the kernel in order to pass values like global
offsets or buffers for printf.  OpenMP, HCC, or other languages may want
to add their own values which differ from OpenCL.

The reason for adding a new opencl environment type is to make it possible for the backend
to distinguish between the ABIs of the higher-level languages and handle them correctly.
It seems cleaner to use the enviroment component for this rather than creating a new
OS type for every combination of low-level runtime / high-level language.

Reviewers: Anastasia, chandlerc

Subscribers: whchung, pekka.jaaskelainen, wdng, yaxunl, llvm-commits

Differential Revision: https://reviews.llvm.org/D24735

llvm-svn: 282218
2016-09-23 00:42:56 +00:00
Petr Hosek
5256e5a7bb [MC] Support skip and count for .incbin directive
These optional arguments are supported by GNU assembler.

Differential Revision: https://reviews.llvm.org/D24714

llvm-svn: 282217
2016-09-23 00:41:06 +00:00
Kostya Serebryany
13b73c7438 [libFuzzer] change ValueBitMap to remember the number of bits in it
llvm-svn: 282216
2016-09-23 00:22:46 +00:00
Quentin Colombet
a1311e08f9 [AArch64][RegisterBankInfo] Switch to TableGen'ed like PartialMapping.
Statically instanciate the most common PartialMappings. This should
be closer to what the code would look like when TableGen support is
added for GlobalISel. As a side effect, this should improve compile
time.

llvm-svn: 282215
2016-09-23 00:14:36 +00:00
Quentin Colombet
02e4ffe509 [RegisterBankInfo] Check that the mapping covers the interesting bits.
In the verify method of the ValueMapping class we used to check that the
mapping exactly matches the bits of the input value. This is problematic
for statically allocated mappings because we would need a different
mapping for each different size of the value that maps on one
instruction. For instance, with such scheme, we would need a different
mapping for a value of size 1, 5, 23 whereas they all end up on a 32-bit
wide instruction.

Therefore, change the verifier to check that the meaningful bits are
covered by the mapping instead of matching them.

llvm-svn: 282214
2016-09-23 00:14:34 +00:00
Quentin Colombet
2a450b9923 [RegisterBankInfo] Use array instead of SmallVector for BreakDown.
This is another step toward TableGen'ed like structures. The BreakDown of
the mapping of the value will be statically computed by TableGen, thus
we only have to point to the right entry in the table instead of
dynamically allocate the mapping for each instruction.

We still support the dynamic allocation through a factory of
PartialMapping to ease the bring-up of the targets while the TableGen
backend is not available.

llvm-svn: 282213
2016-09-23 00:14:30 +00:00
Kostya Serebryany
e7337182e5 [libFuzzer] simplify the crash minimizer; split MaxLen into two: MaxInputLen and MaxMutationLen, allow MaxMutationLen to be less than MaxInputLen
llvm-svn: 282211
2016-09-22 23:16:36 +00:00
Sanjay Patel
3fb981ce63 [InstCombine] fold X urem C -> X < C ? X : X - C when C is big (PR28672)
We already have the udiv variant of this transform, so I think this is ok for 
InstCombine too even though there is an increase in IR instructions. As the 
tests and TODO comments show, the transform can lead to follow-on combines.

This should fix: https://llvm.org/bugs/show_bug.cgi?id=28672

Differential Revision: https://reviews.llvm.org/D24527

llvm-svn: 282209
2016-09-22 22:36:26 +00:00
Davide Italiano
91d9ad7be2 [AsmParser] Remove unused partial template specialization.
llvm-svn: 282206
2016-09-22 22:02:59 +00:00
Vedant Kumar
ad52945c14 [utils] Teach the code coverage prep script about --restrict
Add two options to the code coverage artifact prep script:

  * --use-existing-profdata: Use an existing indexed profile instead of
    merging the same profiles again.
  * --restrict: Restrict the coverage reporting to the given list of
    source directories.

With this in place, we can teach the coverage bot how to prepare
separate reports for each of the llvm tools.

llvm-svn: 282204
2016-09-22 21:49:49 +00:00
Vedant Kumar
03d68ebbdc [llvm-cov] Document some fields in a class (NFC)
llvm-svn: 282203
2016-09-22 21:49:47 +00:00
Vedant Kumar
2e7b123245 [llvm-cov] Add the ability to specify directories of input source files
We've supported restricting coverage reports to a set of files for a
long time. Add support for being able to restrict by entire directories.

I suppose this supersedes D20803.

llvm-svn: 282202
2016-09-22 21:49:43 +00:00
Matthias Braun
650e8168dc MachineScheduler: Slightly simplify release node
llvm-svn: 282201
2016-09-22 21:39:56 +00:00
Matthias Braun
b1e06b237f MachineScheduler: Remove ineffective heuristic; NFC
Currently all nodes get added to the NextSU list when they are released,
so any candidate must be in that list, making the heuristic ineffective.
Remove it for now, we can add it back later in a working fashion if
necessary.

llvm-svn: 282200
2016-09-22 21:39:52 +00:00
Hans Wennborg
397edc9070 Revert r282168 "GVN-hoist: fix store past load dependence analysis (PR30216)"
and also the dependent r282175 "GVN-hoist: do not dereference null pointers"

It's causing compiler crashes building Harfbuzz (PR30499).

llvm-svn: 282199
2016-09-22 21:20:53 +00:00
Krzysztof Parzyszek
a28e3dd9fd [RDF] Add initial support for lane masks in the DFG
Use lane masks for calculating covering and aliasing of register
references.

llvm-svn: 282194
2016-09-22 21:01:24 +00:00
Krzysztof Parzyszek
047695086f [Hexagon] Remove USR_OVF from CtrRegs register class
USR_OVF is a subregister of USR, which is a member of CtrRegs. Having both
a register and its proper subregister in the same register class has bad
consequences for lane mask calculation: based solely on the lane mask info,
USR_OVF would not appear to be a subregister of USR.

llvm-svn: 282192
2016-09-22 20:59:41 +00:00
Krzysztof Parzyszek
4e87f8e468 [RDF] Print the function name for calls in dumps
llvm-svn: 282191
2016-09-22 20:58:19 +00:00
Krzysztof Parzyszek
38eef5294c [RDF] Use uint32_t for register numbers instead of unsigned
llvm-svn: 282190
2016-09-22 20:56:39 +00:00
Arnold Schwaighofer
115971c664 i386 does not support optimized swifterror handling
rdar://28432565

llvm-svn: 282186
2016-09-22 20:06:25 +00:00
Hans Wennborg
d1cad41742 Win64: Don't emit unwind info for "leaf" functions (PR30337)
According to MSDN (see the PR), functions which don't touch any callee-saved
registers (including %rsp) don't need any unwind info.

This patch makes LLVM not emit unwind info for such functions, to save
binary size.

Differential Revision: https://reviews.llvm.org/D24748

llvm-svn: 282185
2016-09-22 19:50:05 +00:00
Zachary Turner
ba26d470c1 Fix build breakage due to typo in cast.
llvm-svn: 282183
2016-09-22 19:21:32 +00:00
Nemanja Ivanovic
07dc6b6937 [PowerPC] Sign extend sub-word values for atomic comparisons
Atomic comparison instructions use the sub-word load instruction on
Power8 and up but the value is not sign extended prior to the signed word
compare instruction. This patch adds that sign extension.

llvm-svn: 282182
2016-09-22 19:06:38 +00:00
Nirav Dave
f3f5f12c53 [DAG] Fix incorrect alignment of ext load.
Correctly use alignment size from loaded size not output value size.

Reviewers: jyknight, tstellarAMD, arsenm

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23356

llvm-svn: 282177
2016-09-22 17:28:43 +00:00
Sebastian Pop
2879352ee0 GVN-hoist: do not dereference null pointers
there may be basic blocks without memory accesses, in which case the
list of accesses is a null pointer.

llvm-svn: 282175
2016-09-22 17:22:58 +00:00
Krzysztof Parzyszek
344cd70c0b [PPC] Set SP after loading data from stack frame, if no red zone is present
Follow-up to r280705: Make sure that the SP is only restored after all data
is loaded from the stack frame, if there is no red zone.

This completes the fix for https://llvm.org/bugs/show_bug.cgi?id=26519.

Differential Revision: https://reviews.llvm.org/D24466

llvm-svn: 282174
2016-09-22 17:22:43 +00:00
Zachary Turner
986cc88263 Speculative fix for build failures due to consumeInteger.
A recent patch added support for consumeInteger() and made
getAsInteger delegate to this function.  A few buildbots are
failing as a result with an assertion failure.  On a hunch,
I tested what happens if I call getAsInteger() on an empty
string, and sure enough it crashes the same way that the
buildbots are crashing.

I confirmed that getAsInteger() on an empty string did not
crash before my patch, so I suspect this to be the cause.

I also added a unit test for the empty string.

llvm-svn: 282170
2016-09-22 15:55:05 +00:00
Sebastian Pop
0a87104c7e GVN-hoist: fix store past load dependence analysis (PR30216)
To hoist stores past loads, we used to search for potential
conflicting loads on the hoisting path by following a MemorySSA
def-def link from the store to be hoisted to the previous
defining memory access, and from there we followed the def-use
chains to all the uses that occur on the hoisting path. The
problem is that the def-def link may point to a store that does
not alias with the store to be hoisted, and so the loads that are
walked may not alias with the store to be hoisted, and even as in
the testcase of PR30216, the loads that may alias with the store
to be hoisted are not visited.

The current patch visits all loads on the path from the store to
be hoisted to the hoisting position and uses the alias analysis
to ask whether the store may alias the load. I was not able to
use the MemorySSA functionality to ask for whether load and
store are clobbered: I'm not sure which function to call, so I
used a call to AA->isNoAlias().

Store past store is still working as before using a MemorySSA
query: I added an extra test to pr30216.ll to make sure store
past store does not regress.

Differential Revision: https://reviews.llvm.org/D24517

llvm-svn: 282168
2016-09-22 15:33:51 +00:00
Sebastian Pop
8b7ceb1130 GVN-hoist: fix typo
llvm-svn: 282165
2016-09-22 15:08:09 +00:00
Zachary Turner
3d1c3fcd78 [Support] Add StringRef::consumeInteger.
StringRef::getInteger() exists and treats the entire string as
an integer of the specified radix, failing if any invalid characters
are encountered or the number overflows.

Sometimes you might have something like "123456foo" and you want
to get the number 123456 and leave the string "foo" remaining.
This is similar to what would be possible by using the standard
runtime library functions strtoul et al and specifying an end
pointer.

This patch adds consumeInteger(), which does exactly that.  It
consumes as much as possible until an invalid character is found,
and modifies the StringRef in place so that upon return only
the portion of the StringRef after the number remains.

Differential Revision: https://reviews.llvm.org/D24778

llvm-svn: 282164
2016-09-22 15:05:19 +00:00
Etienne Bergeron
f1efb9897d [compiler-rt] fix typo in option description [NFC]
llvm-svn: 282163
2016-09-22 14:57:24 +00:00
Sebastian Pop
1b14464087 GVN-hoist: move hoist testcase to GVNHoist dir
llvm-svn: 282161
2016-09-22 14:45:46 +00:00
Sebastian Pop
628c0b289f GVN-hoist: only hoist relevant scalar instructions
Without this patch, GVN-hoist would think that a branch instruction is a scalar instruction
and would try to value number it. The patch filters out all such kind of irrelevant instructions.

A bit frustrating is that there is no easy way to discard all those very infrequent instructions,
a bit like isa<TerminatorInst> that stands for a large family of instructions. I'm thinking that
checking for those very infrequent other instructions would cost us more in compilation time
than just letting those instructions getting numbered, so I'm still thinking that a simpler check:

  if (isa<TerminatorInst>(I))
    return false;

is better than listing all the other less frequent instructions.

Differential Revision: https://reviews.llvm.org/D23929

llvm-svn: 282160
2016-09-22 14:45:40 +00:00
Keith Walker
e6fccf064e Reapplying r281895 (and follow-up r281964) after fixing pr30468.
The additional fix is:

When adding debug information to a lowered phi node in mem2reg
check that we have a valid insertion point after the phi for adding
the debug information.

This change addresses the issue in pr30468 where a lowered phi was
added before a catchswitch and no debug information should be added
after the phi in this case.

Differential Revision: https://reviews.llvm.org/D24797

llvm-svn: 282155
2016-09-22 14:13:25 +00:00
Tim Northover
3841e1ae81 GlobalISel: handle stack-based parameters on AArch64.
llvm-svn: 282153
2016-09-22 13:49:25 +00:00
Anna Thomas
16cf546b7c [RS4GC] Remat in presence of phi and use live value
Summary:

Reviewers:

Subscribers:

llvm-svn: 282150
2016-09-22 13:13:06 +00:00