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48565 Commits

Author SHA1 Message Date
Bill Wendling
d319d42aea Emit the __compact_unwind section first. If there are any frames which weren't 
emitted, emit them next as CIE/FDEs.

llvm-svn: 135807
 2011-07-22 21:18:59 +00:00
Bruno Cardoso Lopes
50a38b479a Fix PR10422 by adding the necessary AVX UCOMISD memory versions to 
load folding logic

llvm-svn: 135801
 2011-07-22 20:53:20 +00:00
Jim Grosbach
9ffa43becc ARM assembly parsing and encoding of SMLAL instruction. 
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
 2011-07-22 20:18:21 +00:00
Jim Grosbach
4f1031662f ARM encoding and assembly parsing of SMLAD{X} instructions. 
Fix encoding of destination register. Add tests.

llvm-svn: 135796
 2011-07-22 20:11:20 +00:00
Bruno Cardoso Lopes
5382a1e65e Add v8f32->v8i32 bitcast. Fixes PR10440 
llvm-svn: 135794
 2011-07-22 19:51:02 +00:00
Rafael Espindola
0c8190c4a3 Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64 
too. Patch by Jeff Muizelaar.

llvm-svn: 135789
 2011-07-22 18:56:05 +00:00
Dan Gohman
734f165c30 Fix x86's XALUO lowering to return its replacement values instead 
of doing the RAUW calls for the overflow value itself. This makes
it more consistent with how the rest of LegalizeDAG works.

llvm-svn: 135788
 2011-07-22 18:45:15 +00:00
Owen Anderson
42c1cb92e5 Fix test failures caused by my so_reg refactoring. 
llvm-svn: 135785
 2011-07-22 18:30:30 +00:00
Jim Grosbach
ebd66f344c ARM assembly parsing and encoding for SMC instruction. 
llvm-svn: 135782
 2011-07-22 18:13:31 +00:00
Jim Grosbach
c80a7c4e75 Clean up a few more comments. 
These instruction definitions are for the assembler, too, not just the
disassembler.

llvm-svn: 135781
 2011-07-22 18:06:01 +00:00
Jim Grosbach
8168e689c0 Tidy up. 
llvm-svn: 135779
 2011-07-22 18:04:10 +00:00
Jim Grosbach
bab60c95e1 Thumb assembly support for SETEND instruction. 
llvm-svn: 135778
 2011-07-22 17:52:23 +00:00
Jim Grosbach
98e7733a08 Tidy up. 
llvm-svn: 135777
 2011-07-22 17:46:13 +00:00
Jim Grosbach
0fe45ec0ed ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.

llvm-svn: 135776
 2011-07-22 17:44:50 +00:00
Jim Grosbach
97f089a499 Tidy up. 
llvm-svn: 135771
 2011-07-22 16:59:04 +00:00
Jay Foad
5ceaa632f9 Fix more MSVC warnings caused by a cases I missed when converting 
ConstantExpr::getGetElementPtr to use ArrayRef.

llvm-svn: 135762
 2011-07-22 08:52:50 +00:00
Jay Foad
42463ed852 Convert IRBuilder::CreateGEP and IRBuilder::CreateInBoundsGEP to use 
ArrayRef.

llvm-svn: 135761
 2011-07-22 08:16:57 +00:00
Chandler Carruth
ace8fa5233 Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs. 
The header file was already properly located. The previous need for it
in Support had to do with the version string printing which was fixed in
r135757.

Also update build dependencies where libraries that needed the
functionality of the Target library (in the form of the TargetRegistry)
were picking it up via Support. This is pretty pervasive, essentially
every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it
depend on Target. All of these were previously just sneaking by.

llvm-svn: 135760
 2011-07-22 08:16:53 +00:00
Jay Foad
e12d8629a8 Fix an MSVC warning, caused by a case I missed when converting 
ConstantExpr::getGetElementPtr to use ArrayRef.

llvm-svn: 135758
 2011-07-22 07:54:01 +00:00
Chandler Carruth
9df16051f4 Move the registered target printing in version strings completely out of 
the Support library. Now its part of the TargetRegistry, and the three
commands that care about this explicitly register this extra bit of
version information.

The set of commands which care was computed by intersecting those which
use the Support library's version string printing and those that
initialize all the registered targets in a way that produces
a meaningful list. The only odd ball out is that 'clang -cc1as -version'
no longer prints the registered targets. I don't think anyone is really
interested in that (especially as the fact that llvm-mc does so is under
a FIXME), but if someone really does want this back I'll happily apply
the same patch there.

llvm-svn: 135757
 2011-07-22 07:50:48 +00:00
Chandler Carruth
0ad63a1326 Move the logic for printing the registered targets into a static 
function on the TargetRegistry. Also clean it up and use the modern LLVM
utility libraries available instead of rolling a few things manually.

llvm-svn: 135756
 2011-07-22 07:50:44 +00:00
Chandler Carruth
6931004b83 Add an extension point to the CommandLine library where clients can 
register extra version information to be printed. This is designed to
allow those tools which link in various targets to also print those
registered targets under --version.

Currently this printing logic is embedded into the Support library
directly; a huge layering violation. This is the first step to hoisting
it out into the tools without adding lots of duplicated code.

llvm-svn: 135755
 2011-07-22 07:50:40 +00:00
NAKAMURA Takumi
b5d972a8c9 lib/Support/Triple.cpp: Recognize "-march=ppc32" to llc properly, as quick hack. 
FIXME: There is an inconsistency. llvm::Triple does not understand "ppc32" and PowerPC/TargetInfo holds "ppc32".
llvm-svn: 135745
 2011-07-22 04:02:22 +00:00
Jakub Staszak
cf5ebedf56 Allow getBlockFreq to return 0. 
llvm-svn: 135742
 2011-07-22 02:24:57 +00:00
Benjamin Kramer
d63be39648 GCC complains about the angle of this line. 
Remove the escaped newline.

llvm-svn: 135739
 2011-07-22 01:02:57 +00:00
Jakub Staszak
50b63cc04e Revert patch which broke some IfConversion tests. 
llvm-svn: 135738
 2011-07-22 00:55:15 +00:00
Jakub Staszak
193dd197eb Fix typo in #include which revealed in the case-sensitive filesystem. 
llvm-svn: 135734
 2011-07-22 00:39:00 +00:00
Bruno Cardoso Lopes
8f30ce017a Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn't 
the way to go. Doing this here will prevent several node matches later,
and would have to force looking all the way through several
VINSERTF128/VEXTRACTF128 chains to optimize simple things.

llvm-svn: 135730
 2011-07-22 00:15:10 +00:00
Bruno Cardoso Lopes
b7b9688aa5 -Inspected a AVX code block added by someone in early Feb. This was never used 
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.

- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.

- Fix a fragile test and make it more useful.

llvm-svn: 135729
 2011-07-22 00:15:07 +00:00
Bruno Cardoso Lopes
1ee6122518 Add a DAGCombine for transforming 128->256 casts into a simple 
vxorps + vinsertf128 pair of instructions

llvm-svn: 135727
 2011-07-22 00:15:00 +00:00
Bruno Cardoso Lopes
7e5f2950cc Introduce a new function to lower 256-bit vectors which are not 
direclty supported and should be promoted and handled by smaller
shuffles

llvm-svn: 135726
 2011-07-22 00:14:56 +00:00
Bruno Cardoso Lopes
71a17c4789 Rename function to be more specific and be more strict about its usage 
llvm-svn: 135725
 2011-07-22 00:14:53 +00:00
Jakub Staszak
bb1d5dc7e7 Use MachineBranchProbabilityInfo instead of MachineLoopInfo in IfConversion. 
llvm-svn: 135724
 2011-07-21 23:48:55 +00:00
Owen Anderson
e34471d064 Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits. 
llvm-svn: 135722
 2011-07-21 23:38:37 +00:00
Dan Gohman
b320950f65 Fix MergeInVectorType to check for vector types with the same alloc 
size but different element types, so that it filters out the cases
that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827.

llvm-svn: 135721
 2011-07-21 23:30:09 +00:00
Jim Grosbach
e56f945492 ARM Asm parser range checking for [0,31] immediates. 
llvm-svn: 135719
 2011-07-21 23:26:25 +00:00
Jakub Staszak
e01d74a920 Add missing getAnalysisUsage in MachineBlockFrequency. 
llvm-svn: 135714
 2011-07-21 22:59:09 +00:00
Jim Grosbach
8d031eeb23 ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
 2011-07-21 22:56:30 +00:00
Jim Grosbach
e96857fd4f ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
 2011-07-21 22:37:43 +00:00
Jim Grosbach
724e527a7a Tidy up. 
llvm-svn: 135706
 2011-07-21 21:26:05 +00:00
Nicolas Geoffray
5cea57ec31 Update generated CPP code with the new API on CallInst::Create and ConstantExpr::getGetElementPtr. 
llvm-svn: 135704
 2011-07-21 20:59:21 +00:00
Jim Grosbach
a860ba338f ARM assembly parsing POP/PUSH mnemonics. 
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.

llvm-svn: 135702
 2011-07-21 19:57:11 +00:00
Oscar Fuentes
c951cb1ef4 Fix CMake build 
llvm-svn: 135698
 2011-07-21 19:10:57 +00:00
Owen Anderson
2e26de13d2 Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowing us to distinguish the encodings that use shifted registers from those that use shifted immediates. This is necessary to allow the fixed-length decoder to distinguish things like BICS vs LDRH. 
llvm-svn: 135693
 2011-07-21 18:54:16 +00:00
Andrew Trick
66db1adfe1 Cleanup: make std::pair usage slightly less indecipherable without actually naming variables! 
llvm-svn: 135684
 2011-07-21 17:37:39 +00:00
Jim Grosbach
5a0277bab7 ARM assembly parsing and encoding for PKHBT and PKHTB instructions. 
llvm-svn: 135682
 2011-07-21 17:23:04 +00:00
Bruno Cardoso Lopes
6934331f4c Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir 
Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.

llvm-svn: 135678
 2011-07-21 16:28:51 +00:00
Jay Foad
42eb18b051 Make better use of ConstantExpr::getGetElementPtr's InBounds parameter. 
llvm-svn: 135676
 2011-07-21 15:15:37 +00:00
Jay Foad
d4458dd707 Convert ConstantExpr::getGetElementPtr and 
ConstantExpr::getInBoundsGetElementPtr to use ArrayRef.

llvm-svn: 135673
 2011-07-21 14:31:17 +00:00
Chris Lattner
c4ab50bd33 move tier out of an anonymous namespace, it doesn't make sense 
to for it to be an an anon namespace and be in a header.

Eliminate some extraenous uses of tie.

llvm-svn: 135669
 2011-07-21 06:21:31 +00:00
Bruno Cardoso Lopes
3691063149 - Register v16i16 as valid VR256 register class 
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

llvm-svn: 135663
 2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes
ba1a2a9135 Add support for 256-bit versions of VPERMIL instruction. This is a new 
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

llvm-svn: 135662
 2011-07-21 01:55:47 +00:00
Bruno Cardoso Lopes
b16371a45e Improve splat promotion to handle AVX types: v32i8 and v16i16. Also 
refactor the code and add a bunch of comments. The final shuffle
emitted by handling 256-bit types is suitable for the VPERM shuffle
instruction which is going to be introduced in a next commit (with
a testcase which cover this commit)

llvm-svn: 135661
 2011-07-21 01:55:42 +00:00
Bruno Cardoso Lopes
194507cc77 Add aditional patterns for vextractf128 instruction 
llvm-svn: 135660
 2011-07-21 01:55:39 +00:00
Bruno Cardoso Lopes
14c800c1e3 Add aditional patterns for vinsertf128 instruction 
llvm-svn: 135659
 2011-07-21 01:55:36 +00:00
Bruno Cardoso Lopes
a8244d4444 Add v16i16 type to VR256 class 
llvm-svn: 135658
 2011-07-21 01:55:33 +00:00
Bruno Cardoso Lopes
e0d5bd467f Move code around. No functionality changes 
llvm-svn: 135657
 2011-07-21 01:55:30 +00:00
Bruno Cardoso Lopes
60093b6104 Tidy up code 
llvm-svn: 135656
 2011-07-21 01:55:27 +00:00
Andrew Trick
1f9b4f8617 LSR, correct fix for rdar://9786536. Silly casting bug. 
llvm-svn: 135654
 2011-07-21 01:45:54 +00:00
Andrew Trick
ebf9ee5200 LSR must sometimes sign-extend before generating double constants. 
rdar://9786536

llvm-svn: 135650
 2011-07-21 01:05:01 +00:00
Bill Wendling
1f46862df8 Mark instructions which are part of the frame setup with the MachineInstr::FrameSetup flag. 
llvm-svn: 135645
 2011-07-21 00:44:56 +00:00
Andrew Trick
4b641bba84 LSR crashes on an empty IVUsers list. 
rdar://9786536

llvm-svn: 135644
 2011-07-21 00:40:04 +00:00
Evan Cheng
882618fe7d X86 is the only target that uses coff format. This should fixes test failures running on Windows, Cygwin, or MingW hosts. 
llvm-svn: 135639
 2011-07-20 23:53:54 +00:00
Evan Cheng
bff5f78cb5 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. 
llvm-svn: 135636
 2011-07-20 23:34:39 +00:00
Bill Wendling
4958d250c9 Remove unused function. 
llvm-svn: 135635
 2011-07-20 23:07:42 +00:00
Bill Wendling
55eb4a26d9 Remove the now defunct getCompactUnwindEncoding method from the frame lowering code. 
llvm-svn: 135634
 2011-07-20 23:04:09 +00:00
Devang Patel
bf27de8340 Refactor. 
llvm-svn: 135633
 2011-07-20 23:00:27 +00:00
Devang Patel
284b502be9 There are two ways to map a variable to its lexical scope. Lexical scope information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode. 
llvm-svn: 135629
 2011-07-20 22:18:50 +00:00
Eli Friedman
c18314afef Clean up includes of llvm/Analysis/ConstantFolding.h so it's included where it's used and not included where it isn't. 
llvm-svn: 135628
 2011-07-20 21:57:23 +00:00
Devang Patel
9914fe1aca While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value. 
llvm-svn: 135627
 2011-07-20 21:57:04 +00:00
Jim Grosbach
572868e146 ARM PKH shift ammount operand printing tweaks. 
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.

llvm-svn: 135626
 2011-07-20 21:40:26 +00:00
Eli Friedman
f98434b2c7 Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef. 
llvm-svn: 135625
 2011-07-20 21:37:47 +00:00
Jim Grosbach
fbaaa3ae98 Tidy up a bit. 
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.

llvm-svn: 135617
 2011-07-20 20:49:03 +00:00
Jim Grosbach
94a88152c9 ARM: Tidy up representation of PKH instruction. 
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.

llvm-svn: 135616
 2011-07-20 20:32:09 +00:00
Benjamin Kramer
575cdb54f1 Fix cmake again :) 
llvm-svn: 135613
 2011-07-20 20:00:06 +00:00
Evan Cheng
c9bc5a9011 Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. 
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.

llvm-svn: 135611
 2011-07-20 19:50:42 +00:00
Eli Friedman
7776a468cf Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. 
llvm-svn: 135607
 2011-07-20 19:36:11 +00:00
Jim Grosbach
1514063b5f ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596
 2011-07-20 18:20:31 +00:00
Eli Friedman
3af0eb7b5f PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS. 
llvm-svn: 135595
 2011-07-20 18:14:33 +00:00
Benjamin Kramer
7636a9969a Initialize the EHFrameSection pointer to zero. 
This should fix the spurious buildbot errors.

llvm-svn: 135594
 2011-07-20 18:13:23 +00:00
Jay Foad
03130446b5 Fix a GCC warning. 
llvm-svn: 135581
 2011-07-20 08:15:21 +00:00
Evan Cheng
55d7fcc5f7 - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
 2011-07-20 07:51:56 +00:00
Evan Cheng
abb07a0c9d Include MCRegisterInfo to eliminate a compilation warning. 
llvm-svn: 135575
 2011-07-20 06:54:19 +00:00
Francois Pichet
74e35bf8ec Fix the CMake build. 
llvm-svn: 135573
 2011-07-20 06:35:24 +00:00
Evan Cheng
380dc98371 Add MCObjectFileInfo and sink the MCSections initialization code from 
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569
 2011-07-20 05:58:47 +00:00
Andrew Trick
57280c0f11 indvars: Added getInsertPointForUses to find a valid place to truncate the IV. 
llvm-svn: 135568
 2011-07-20 05:32:06 +00:00
Andrew Trick
9c4333db13 indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-use 
info. Holding Use* pointers is bad form even though it happened to
work in this case.

llvm-svn: 135566
 2011-07-20 04:39:24 +00:00
NAKAMURA Takumi
19d48c106d X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin. 
llvm-svn: 135564
 2011-07-20 04:02:20 +00:00
Eric Christopher
51af0c896c Extra semi-colon. 
llvm-svn: 135561
 2011-07-20 02:44:39 +00:00
Andrew Trick
ee2d72e5f1 indvars -disable-iv-rewrite fix: derived GEP IVs 
llvm-svn: 135558
 2011-07-20 02:08:58 +00:00
Benjamin Kramer
679af0868f Don't leak CodeGenInfos. 
llvm-svn: 135555
 2011-07-20 01:27:58 +00:00
Akira Hatanaka
a9cbfe8f88 Change name of class. 
llvm-svn: 135550
 2011-07-20 00:53:09 +00:00
Akira Hatanaka
f61c905927 Define classes for definitions of atomic instructions. 
llvm-svn: 135546
 2011-07-20 00:23:01 +00:00
Akira Hatanaka
a50bbdfe15 Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Evan Cheng
9a80b0a7e6 Fix an obvious typo that's preventing x86 (32-bit) from using .literal16. 
llvm-svn: 135535
 2011-07-19 23:14:32 +00:00
Eli Friedman
f809f44cf5 PR10386: Don't try to split an edge from an indirectbr. 
llvm-svn: 135534
 2011-07-19 22:59:41 +00:00
Jim Grosbach
e70c8eb49a Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
 2011-07-19 22:45:10 +00:00
Devang Patel
65afdd27d0 Distinguish between two copies of one inlined variable. 
llvm-svn: 135528
 2011-07-19 22:31:15 +00:00
Jim Grosbach
720b8c6578 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
 2011-07-19 21:59:29 +00:00
Owen Anderson
ad0f17c102 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM. 
llvm-svn: 135524
 2011-07-19 21:06:00 +00:00
Akira Hatanaka
cccc5fca34 Change variable name. 
llvm-svn: 135522
 2011-07-19 20:56:53 +00:00
Jim Grosbach
66af8b4a40 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. 
Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521
 2011-07-19 20:35:35 +00:00
Akira Hatanaka
14e517df43 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
 2011-07-19 20:34:00 +00:00
Akira Hatanaka
b4db39fa83 Use descriptive variable names. 
llvm-svn: 135514
 2011-07-19 20:11:17 +00:00
Jim Grosbach
9debba28ed ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513
 2011-07-19 20:10:31 +00:00
Jim Grosbach
7e61a1ecf2 Tidy up. 
llvm-svn: 135507
 2011-07-19 19:47:11 +00:00
Jim Grosbach
8ebe7d700a Tighten conditional for 'mov' cc_out. 
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.

llvm-svn: 135506
 2011-07-19 19:45:44 +00:00
Devang Patel
5a4bb57ec5 Reapply r135457. This needs llvm-gcc change, that I forgot to check-in yesterday. 
llvm-svn: 135504
 2011-07-19 19:41:54 +00:00
Jim Grosbach
294b83e3e2 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
 2011-07-19 19:13:28 +00:00
Jim Grosbach
14e26dd644 Remove unused code. 
cc_out and pred operands are added during parsing via custom C++ now.

llvm-svn: 135497
 2011-07-19 18:32:48 +00:00
Akira Hatanaka
19c16a84ff Fix comments. 
llvm-svn: 135496
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
f59cbeec14 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
57d207bc7b Separate code that modifies control flow from code that adds instruction to 
basic blocks.

llvm-svn: 135490
 2011-07-19 17:09:53 +00:00
Jim Grosbach
31cda4ed6d ARM range checking for so_imm operands in assembly parsing. 
llvm-svn: 135489
 2011-07-19 16:50:30 +00:00
Bob Wilson
7c9092c9aa Revert "Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block." 
This reverts commit 9fec5e346efdf744b151ae6604f912908315fa7a.

llvm-svn: 135486
 2011-07-19 16:32:50 +00:00
Jay Foad
6d007bef3c Convert ConstantFoldGetElementPtr to use ArrayRef. 
llvm-svn: 135483
 2011-07-19 15:30:30 +00:00
Jay Foad
bbbf29aab7 Convert SimplifyGEPInst to use ArrayRef. 
llvm-svn: 135482
 2011-07-19 15:07:52 +00:00
Jay Foad
83a0e1fa99 Convert gep_type_begin and gep_type_end to use ArrayRef. 
llvm-svn: 135481
 2011-07-19 14:42:50 +00:00
Jay Foad
0974b71f17 Convert TargetData::getIndexedOffset to use ArrayRef. 
llvm-svn: 135478
 2011-07-19 14:01:37 +00:00
Jay Foad
ae5894c5cc Use ArrayRef in ConstantFoldInstOperands and ConstantFoldCall. 
llvm-svn: 135477
 2011-07-19 13:32:40 +00:00
Richard Osborne
b469141419 Add intrinsics for the zext / sext instructions. 
llvm-svn: 135476
 2011-07-19 13:28:50 +00:00
Richard Osborne
50303e0d38 Add intrinsics for the testct, testwct instructions. 
llvm-svn: 135475
 2011-07-19 13:00:40 +00:00
Richard Osborne
409c0d7768 Add intrinsics for the peek and endin instructions. 
llvm-svn: 135474
 2011-07-19 12:50:25 +00:00
Evan Cheng
bfc0cac54d Introduce MCCodeGenInfo, which keeps information that can affect codegen 
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468
 2011-07-19 06:37:02 +00:00
Akira Hatanaka
ad3687eb3a Make EmitAtomic functions return the correct MachineBasicBlocks so that 
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465
 2011-07-19 03:42:13 +00:00
Akira Hatanaka
55b8d79a52 Do not insert instructions in reverse order. 
llvm-svn: 135464
 2011-07-19 03:14:58 +00:00
Devang Patel
e50d45c876 Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block. 
llvm-svn: 135457
 2011-07-19 01:03:32 +00:00
Devang Patel
72886ba8d8 Revert r135423. 
llvm-svn: 135454
 2011-07-19 00:28:24 +00:00
Bill Wendling
cd5cb5b44e Micro-opt: Only emit compact unwind if there is a compact unwind encoding to emit. 
llvm-svn: 135452
 2011-07-19 00:09:25 +00:00
Bill Wendling
8dd021da20 Use the CompactUnwindEncoding from the Frame, if it's defined. 
llvm-svn: 135451
 2011-07-19 00:06:12 +00:00
Bill Wendling
71a83a3b30 Add a frame with the compact unwind encoding if it exists. 
llvm-svn: 135450
 2011-07-19 00:02:51 +00:00
Bill Wendling
6211e2602f Add a method to set compact unwind encoding information in a frame. 
llvm-svn: 135449
 2011-07-19 00:01:42 +00:00
Bill Wendling
b1d5a0798a Rename CompactEncoding to CompactUnwindEncoding. 
llvm-svn: 135448
 2011-07-19 00:00:58 +00:00
Sean Callanan
b5cc61ce9a Fixed a bug where the MC subtarget information 
wasn't being initialized by the enhanced disassembler,
leading to assertion failures. 

llvm-svn: 135447
 2011-07-19 00:00:41 +00:00
Bill Wendling
203796ee7a Move the compact encoding from the target-specific library to the code-gen 
library.

llvm-svn: 135443
 2011-07-18 23:38:40 +00:00
Owen Anderson
27021374f8 Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. 
llvm-svn: 135442
 2011-07-18 23:25:34 +00:00
Evan Cheng
5ad7d33696 Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of the 
use of TargetFrameLowering in TargetAsmInfo.

llvm-svn: 135439
 2011-07-18 22:32:12 +00:00
Evan Cheng
10c6820ff4 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 
better location welcome).

llvm-svn: 135438
 2011-07-18 22:29:13 +00:00
Owen Anderson
b32dac81e0 Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause decoding conflicts in the new-style disassembler. 
llvm-svn: 135434
 2011-07-18 22:14:02 +00:00
Jeffrey Yasskin
2e0f2a0985 Add APInt(numBits, ArrayRef<uint64_t> bigVal) constructor to prevent future ambiguity 
errors like the one corrected by r135261.  Migrate all LLVM callers of the old
constructor to the new one.

llvm-svn: 135431
 2011-07-18 21:45:40 +00:00
Andrew Trick
ff306f7c8b Compiler warning. 
llvm-svn: 135426
 2011-07-18 21:15:03 +00:00
Evan Cheng
561d71ce7b Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424
 2011-07-18 20:57:22 +00:00
Devang Patel
389cb9d8c6 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. 
[take 2]

llvm-svn: 135423
 2011-07-18 20:55:23 +00:00
Andrew Trick
ba37b6516a indvars: LinearFunctionTestReplace for non-canonical IVs. 
For -disable-iv-rewrite, perform LFTR without generating a new
"canonical" induction variable. Instead find the "best" existing
induction variable for use in the loop exit test and compute the final
value of that IV for use in the new loop exit test. In short,
convert to a simple eq/ne exit test as long as it's cheap to do so.

llvm-svn: 135420
 2011-07-18 20:32:31 +00:00
Akira Hatanaka
52263f51f1 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
llvm-svn: 135418
 2011-07-18 19:58:59 +00:00
Akira Hatanaka
79f38f0ae7 Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
 2011-07-18 18:52:12 +00:00
Owen Anderson
aadc53ca80 Re-apply r135319 with a fix for the constant island pass. 
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414
 2011-07-18 18:50:52 +00:00
Jakob Stoklund Olesen
89e84069d2 Fix a crash when building 177.mesa for armv6. 
When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.

We need the value number entering the instruction.

<rdar://problem/9793765>

llvm-svn: 135413
 2011-07-18 18:47:13 +00:00
Andrew Trick
40113d052b indvars: Added verification that LFTR and other indvars goodness does 
not interfere with BackedgeTakenCount computation.

llvm-svn: 135412
 2011-07-18 18:44:20 +00:00
Andrew Trick
111d0bc134 indvars: Added isHighCostExpansion. Avoid generating extra ops in the 
preheader for the sole purpose of LFTR, since LFTR itself is usually not
a clear optimization.

llvm-svn: 135409
 2011-07-18 18:21:35 +00:00