Stanislav Mekhanoshin
3e11a165dc
[AMDGPU] gfx1011/gfx1012 targets
...
Differential Revision: https://reviews.llvm.org/D63307
llvm-svn: 363344
2019-06-14 00:33:31 +00:00
Dmitry Preobrazhensky
559fcce292
[AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions
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See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839
Differential Revision: https://reviews.llvm.org/D45249
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329408
2018-04-06 15:48:39 +00:00
Dmitry Preobrazhensky
4ab10f3f40
[AMDGPU][MC][GFX9] Added s_dcache_discard* instructions
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See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838
Differential Revision: https://reviews.llvm.org/D45247
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 329397
2018-04-06 15:08:42 +00:00
Dmitry Preobrazhensky
5f173c78ac
[AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions
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Fixed a bug which caused Tablegen crash.
See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837
Differential Revision: https://reviews.llvm.org/D45085
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328983
2018-04-02 16:10:25 +00:00
Nico Weber
5caaf5b955
Revert r328975, it makes TableGen assert on the bots.
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llvm-svn: 328978
2018-04-02 14:20:23 +00:00
Dmitry Preobrazhensky
6774d8f2ab
[AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions
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See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837
Differential Revision: https://reviews.llvm.org/D45085
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328975
2018-04-02 13:52:23 +00:00
Dmitry Preobrazhensky
585626cbac
[AMDGPU][MC][GFX9] Added s_scratch* instructions
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See bug 36836: https://bugs.llvm.org/show_bug.cgi?id=36836
Differential Revision: https://reviews.llvm.org/D44832
Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 328704
2018-03-28 14:08:03 +00:00
Matt Arsenault
501bdb609f
AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions
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Fixes assembler regressions.
llvm-svn: 289230
2016-12-09 17:49:11 +00:00
Sam Kolton
7488a77196
[AMDGPU] Disassembler: fix s_buffer_store_dword instructions
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Summary: s_buffer_store_dword instructions sdata operand was called sdst in encoding. This caused disassembler to fail.
Reviewers: tstellarAMD, vpykhtin, artem.tamazov
Subscribers: arsenm, nhaehnle, rampitec
Differential Revision: https://reviews.llvm.org/D27100
llvm-svn: 288657
2016-12-05 09:58:51 +00:00
Matt Arsenault
a0090a0113
AMDGPU: Add definitions for scalar store instructions
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Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.
This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.
llvm-svn: 285463
2016-10-28 21:55:15 +00:00
Nikolay Haustov
bade203fd0
[AMDGPU] Assembler: SOP* instruction fixes
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s_bitset0_b64, s_bitset1_b64 has 32-bit src0, not 64-bit.
s_rfe_b64 has just one destination operand and no source.
Uncomment S_BITCMP* and S_SETVSKIP, adjust SOPC_* classes for that.
Add s_memrealtime test and change comments in smem.s to follow common style.
Change test for s_memtime to use non-zero register to make it really test encoding.
Add tests for s_buffer_load*.
Add tests for SOPC instructions (same for SI and VI)
Differential Revision: http://reviews.llvm.org/D18040
llvm-svn: 263420
2016-03-14 11:17:19 +00:00
Matt Arsenault
4f500cff99
AMDGPU: Add s_dcache_* instructions
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llvm-svn: 248533
2015-09-24 19:52:27 +00:00
