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e94b35dc41
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164 Commits

Author SHA1 Message Date
Johnny Chen
e94b35dc41 Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was not properly handled. 
rdar://problem/9276427

llvm-svn: 129456
 2011-04-13 17:51:02 +00:00
Johnny Chen
5ae9980472 Add sanity check for Ld/St Dual forms of Thumb2 instructions. 
rdar://problem/9273947

llvm-svn: 129411
 2011-04-12 23:31:00 +00:00
Johnny Chen
e3c070e904 The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391
 2011-04-12 21:41:51 +00:00
Johnny Chen
4450794a69 Add bad register checks for Thumb2 Ld/St instructions. 
rdar://problem/9269047

llvm-svn: 129387
 2011-04-12 21:17:51 +00:00
Johnny Chen
4435fc93c9 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.

llvm-svn: 129377
 2011-04-12 18:48:00 +00:00
Johnny Chen
aaaa46cee2 Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 
llvm-svn: 129365
 2011-04-12 17:09:04 +00:00
Johnny Chen
58713f0ec2 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681

llvm-svn: 129325
 2011-04-12 00:14:49 +00:00
Johnny Chen
443a6902bf Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838

llvm-svn: 129320
 2011-04-11 23:33:30 +00:00
Johnny Chen
77f484c5df Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265

llvm-svn: 129298
 2011-04-11 21:14:35 +00:00
Johnny Chen
77dc5a7187 Trivial comment fix. 
llvm-svn: 129288
 2011-04-11 18:51:50 +00:00
Johnny Chen
b07cb8fee1 Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.

llvm-svn: 129286
 2011-04-11 18:34:12 +00:00
Kevin Enderby
6e09a5d065 Adding support for printing operands symbolically to llvm's public 'C' 
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284
 2011-04-11 18:08:50 +00:00
Matt Beaumont-Gay
16d2e58f1d Fix an apparent typo that made GCC complain 
llvm-svn: 129160
 2011-04-08 21:59:49 +00:00
Johnny Chen
18f79bbaca Check opcoe (dmb, dsb) instead of bitfields matching. 
llvm-svn: 129148
 2011-04-08 20:03:46 +00:00
Johnny Chen
e2464aa24a Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565

llvm-svn: 129147
 2011-04-08 19:41:22 +00:00
Johnny Chen
5b7854afa5 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634

llvm-svn: 129146
 2011-04-08 19:18:07 +00:00
Johnny Chen
16ed2c18a0 Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117
 2011-04-08 00:29:09 +00:00
Johnny Chen
5d23dd2116 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.

llvm-svn: 129098
 2011-04-07 19:28:58 +00:00
Johnny Chen
7198a60b9a Add sanity checking for invalid register encodings for saturating instructions. 
llvm-svn: 129096
 2011-04-07 19:02:08 +00:00
Johnny Chen
ecc113f223 Add some more comments about checkings of invalid register numbers. 
And two test cases.

llvm-svn: 129090
 2011-04-07 18:33:19 +00:00
Johnny Chen
4c81015af7 Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844

llvm-svn: 129050
 2011-04-07 01:37:34 +00:00
Johnny Chen
1f028bb23e The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047
 2011-04-07 01:05:52 +00:00
Johnny Chen
523f8f38f7 Should also check SMLAD for invalid register values. 
rdar://problem/9246650

llvm-svn: 129042
 2011-04-07 00:50:25 +00:00
Johnny Chen
81aa7d84be A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^

llvm-svn: 129033
 2011-04-06 22:14:48 +00:00
Johnny Chen
96fd9620c8 A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027
 2011-04-06 20:49:02 +00:00
Johnny Chen
b3130a03a7 Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015
 2011-04-06 18:27:46 +00:00
Johnny Chen
765dec3867 Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
 2011-04-06 01:18:32 +00:00
Johnny Chen
48b39632aa Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register 
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

llvm-svn: 128958
 2011-04-05 23:28:00 +00:00
Johnny Chen
359b9a2331 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949
 2011-04-05 22:57:07 +00:00
Johnny Chen
cf11408b65 ARM disassembler was erroneously accepting an invalid RSC instruction. 
Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945
 2011-04-05 22:18:07 +00:00
Johnny Chen
6e1367d5dd ARM disassembler was erroneously accepting an invalid LSL instruction. 
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941
 2011-04-05 21:49:44 +00:00
Johnny Chen
b50ab34083 The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. 
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

llvm-svn: 128922
 2011-04-05 20:32:23 +00:00
Johnny Chen
4a15bdc1aa ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. 
llvm-svn: 128913
 2011-04-05 19:42:11 +00:00
Jim Grosbach
7bdaed671d Make second source operand of LDRD pre/post explicit. 
Finish what r128736 started.

llvm-svn: 128903
 2011-04-05 18:40:13 +00:00
Johnny Chen
626c0a35f6 Check for invalid register encodings for UMAAL and friends where: 
if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202

llvm-svn: 128895
 2011-04-05 17:43:10 +00:00
Johnny Chen
eb8e7684b9 RFE encoding should also specify the "should be" encoding bits. 
rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE

Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.

llvm-svn: 128859
 2011-04-04 23:39:08 +00:00
Johnny Chen
7fb247299a Fix incorrect alignment for NEON VST2b32_UPD. 
rdar://problem/9225433

llvm-svn: 128841
 2011-04-04 20:35:31 +00:00
Bruno Cardoso Lopes
74363376e4 - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT 
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

llvm-svn: 128832
 2011-04-04 17:18:19 +00:00
Johnny Chen
dcd29e054c Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; 
instead of the second operand in addrmode_imm12.

rdar://problem/9225289

llvm-svn: 128757
 2011-04-02 02:24:54 +00:00
Johnny Chen
65fe34ae00 Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction 
as invalid.

llvm-svn: 128734
 2011-04-01 20:21:38 +00:00
Johnny Chen
17f1f7c322 Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). 
rdar://problem/9219356

llvm-svn: 128722
 2011-04-01 18:26:38 +00:00
Bruno Cardoso Lopes
d285a7f27e Apply again changes to support ARM memory asm parsing. I removed 
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128689
 2011-03-31 23:26:08 +00:00
Johnny Chen
0bb797b2f3 Add BLXi to the instruction table for disassembly purpose. 
A8.6.23 BLX (immediate)

rdar://problem/9212921

llvm-svn: 128644
 2011-03-31 17:53:50 +00:00
Bruno Cardoso Lopes
392dbfd384 Revert r128632 again, until I figure out what break the tests 
llvm-svn: 128635
 2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes
3b2f5421ac Reapply r128585 without generating a lib depedency cycle. An updated log: 
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632
 2011-03-31 14:52:28 +00:00
Owen Anderson
d73041e884 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. 
llvm-svn: 128461
 2011-03-29 16:45:53 +00:00
Johnny Chen
8b921cebc6 Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. 
Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.

llvm-svn: 128417
 2011-03-28 18:41:58 +00:00
Johnny Chen
61713b9c16 Fixed the t2PLD and friends disassembly and add two test cases. 
llvm-svn: 128322
 2011-03-26 01:32:48 +00:00
Johnny Chen
75c4627aea Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID. 
Also add some test cases.

rdar://problem/9189829

llvm-svn: 128304
 2011-03-25 22:19:07 +00:00
Johnny Chen
5b840e19ef DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases. 
rdar://problem/9182892

llvm-svn: 128299
 2011-03-25 19:35:37 +00:00