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Author SHA1 Message Date
Chris Lattner
288e5b0a7d Expose the LiveInterval interfaces as public headers. 
llvm-svn: 23400
 2005-09-21 04:19:09 +00:00
Chris Lattner
8465e88d0f Recommend what I actually test 
llvm-svn: 23398
 2005-09-21 03:56:26 +00:00
Chris Lattner
07cf4f249d Start threading across blocks with code in them, so long as the code does 
not define a value that is used outside of it's block.  This catches many
more simplifications, e.g. 854 in 176.gcc, 137 in vpr, etc.

This implements branch-phi-thread.ll:test3.ll

llvm-svn: 23397
 2005-09-20 01:48:40 +00:00
Chris Lattner
e944688f8b make this test harder: add a case where instructions are in the bb to be 
threaded over

llvm-svn: 23396
 2005-09-20 01:43:41 +00:00
Chris Lattner
44a9487815 Implement merging of blocks with the same condition if the block has multiple 
predecessors.  This implements branch-phi-thread.ll::test1

llvm-svn: 23395
 2005-09-20 00:43:16 +00:00
Chris Lattner
5ab7f9420a new testcase 
llvm-svn: 23394
 2005-09-20 00:41:55 +00:00
Chris Lattner
4013184d6b Reject a case we don't handle yet 
llvm-svn: 23393
 2005-09-19 23:57:04 +00:00
Chris Lattner
642f0d6aea remove debugging code :-/ 
llvm-svn: 23392
 2005-09-19 23:50:15 +00:00
Chris Lattner
34785e2d43 Implement SimplifyCFG/branch-phi-thread.ll, the most trivial case of threading 
control across branches with determined outcomes.  More generality to follow.
This triggers a couple thousand times in specint.

llvm-svn: 23391
 2005-09-19 23:49:37 +00:00
Chris Lattner
2e29152408 new testcase. 
llvm-svn: 23390
 2005-09-19 23:48:04 +00:00
Nate Begeman
236df45f1b Stub out the rest of the DAG Combiner. Just need to fill in the 
select_cc bits and then wrap it in a convenience function for  use with
regular select.

llvm-svn: 23389
 2005-09-19 22:34:01 +00:00
Chris Lattner
59dd979162 Teach the local spiller to turn stack slot loads into register-register copies 
when possible, avoiding the load (and avoiding the copy if the value is already
in the right register).

This patch came about when I noticed code like the following being generated:

  store R17 -> [SS1]
  ...blah...
  R4 = load [SS1]

This was causing an LSU reject on the G5.  This problem was due to the register
allocator folding spill code into a reg-reg copy (producing the load), which
prevented the spiller from being able to rewrite the load into a copy, despite
the fact that the value was already available in a register.  In the case
above, we now rip out the R4 load and replace it with a R4 = R17 copy.

This speeds up several programs on X86 (which spills a lot :) ), e.g.
smg2k from 22.39->20.60s, povray from 12.93->12.66s, 168.wupwise from
68.54->53.83s (!), 197.parser from 7.33->6.62s (!), etc.  This may have a larger
impact in some cases on the G5 (by avoiding LSU rejects), though it probably
won't trigger as often (less spilling in general).

Targets that implement folding of loads/stores into copies should implement
the isLoadFromStackSlot hook to get this.

llvm-svn: 23388
 2005-09-19 06:56:21 +00:00
Chris Lattner
4a8f6d97ff Implement the isLoadFromStackSlot interface 
llvm-svn: 23387
 2005-09-19 05:23:44 +00:00
Chris Lattner
e40e2d4ec3 Refactor this code a bit and make it more general. This now compiles: 
struct S { unsigned int i : 6, j : 11, k : 15; } b;
void plus2 (unsigned int x) { b.j += x; }

To:

_plus2:
        lis r2, ha16(L_b$non_lazy_ptr)
        lwz r2, lo16(L_b$non_lazy_ptr)(r2)
        lwz r4, 0(r2)
        slwi r3, r3, 6
        add r3, r4, r3
        rlwimi r3, r4, 0, 26, 14
        stw r3, 0(r2)
        blr


instead of:

_plus2:
        lis r2, ha16(L_b$non_lazy_ptr)
        lwz r2, lo16(L_b$non_lazy_ptr)(r2)
        lwz r4, 0(r2)
        rlwinm r5, r4, 26, 21, 31
        add r3, r5, r3
        rlwimi r4, r3, 6, 15, 25
        stw r4, 0(r2)
        blr

by eliminating an 'and'.

I'm pretty sure this is as small as we can go :)

llvm-svn: 23386
 2005-09-18 07:22:02 +00:00
Chris Lattner
024a1c1a46 Compile 
struct S { unsigned int i : 6, j : 11, k : 15; } b;
void plus2 (unsigned int x) {
  b.j += x;
}

to:

plus2:
        mov %EAX, DWORD PTR [b]
        mov %ECX, %EAX
        and %ECX, 131008
        mov %EDX, DWORD PTR [%ESP + 4]
        shl %EDX, 6
        add %EDX, %ECX
        and %EDX, 131008
        and %EAX, -131009
        or %EDX, %EAX
        mov DWORD PTR [b], %EDX
        ret

instead of:

plus2:
        mov %EAX, DWORD PTR [b]
        mov %ECX, %EAX
        shr %ECX, 6
        and %ECX, 2047
        add %ECX, DWORD PTR [%ESP + 4]
        shl %ECX, 6
        and %ECX, 131008
        and %EAX, -131009
        or %ECX, %EAX
        mov DWORD PTR [b], %ECX
        ret

llvm-svn: 23385
 2005-09-18 06:30:59 +00:00
Chris Lattner
3cd5e466ee Generalize this transform, using MaskedValueIsZero, allowing us to compile: 
struct S { unsigned int i : 6, j : 11, k : 15; } b;
void plus3 (unsigned int x) { b.k += x; }

To:

plus3:
        mov %EAX, DWORD PTR [%ESP + 4]
        shl %EAX, 17
        add DWORD PTR [b], %EAX
        ret

instead of:

plus3:
        mov %EAX, DWORD PTR [%ESP + 4]
        shl %EAX, 17
        mov %ECX, DWORD PTR [b]
        add %EAX, %ECX
        and %EAX, -131072
        and %ECX, 131071
        or %ECX, %EAX
        mov DWORD PTR [b], %ECX
        ret

llvm-svn: 23384
 2005-09-18 06:02:59 +00:00
Chris Lattner
b70b011734 fix typeo 
llvm-svn: 23383
 2005-09-18 05:25:20 +00:00
Chris Lattner
7fda14c978 Remove unintentionally committed code 
llvm-svn: 23382
 2005-09-18 05:12:51 +00:00
Chris Lattner
ae35713f00 implement shift.ll:test25. This compiles: 
struct S { unsigned int i : 6, j : 11, k : 15; } b;
void plus3 (unsigned int x) {
  b.k += x;
}

to:

_plus3:
        lis r2, ha16(L_b$non_lazy_ptr)
        lwz r2, lo16(L_b$non_lazy_ptr)(r2)
        lwz r3, 0(r2)
        rlwinm r4, r3, 0, 0, 14
        add r4, r4, r3
        rlwimi r4, r3, 0, 15, 31
        stw r4, 0(r2)
        blr

instead of:

_plus3:
        lis r2, ha16(L_b$non_lazy_ptr)
        lwz r2, lo16(L_b$non_lazy_ptr)(r2)
        lwz r4, 0(r2)
        srwi r5, r4, 17
        add r3, r5, r3
        slwi r3, r3, 17
        rlwimi r3, r4, 0, 15, 31
        stw r3, 0(r2)
        blr

llvm-svn: 23381
 2005-09-18 05:12:10 +00:00
Chris Lattner
7e94dfdc90 new testcase 
llvm-svn: 23380
 2005-09-18 05:10:39 +00:00
Chris Lattner
fa22870351 Implement add.ll:test29. Codegening: 
struct S { unsigned int i : 6, j : 11, k : 15; } b;
void plus1 (unsigned int x) {
  b.i += x;
}

as:
_plus1:
        lis r2, ha16(L_b$non_lazy_ptr)
        lwz r2, lo16(L_b$non_lazy_ptr)(r2)
        lwz r4, 0(r2)
        add r3, r4, r3
        rlwimi r3, r4, 0, 0, 25
        stw r3, 0(r2)
        blr

instead of:

_plus1:
        lis r2, ha16(L_b$non_lazy_ptr)
        lwz r2, lo16(L_b$non_lazy_ptr)(r2)
        lwz r4, 0(r2)
        rlwinm r5, r4, 0, 26, 31
        add r3, r5, r3
        rlwimi r3, r4, 0, 0, 25
        stw r3, 0(r2)
        blr

llvm-svn: 23379
 2005-09-18 04:24:45 +00:00
Chris Lattner
dd10722054 new testcase 
llvm-svn: 23378
 2005-09-18 04:22:59 +00:00
Chris Lattner
c96a222019 remove debug output 
llvm-svn: 23377
 2005-09-18 03:50:25 +00:00
Chris Lattner
1466ade38b Implement or.ll:test21. This teaches instcombine to be able to turn this: 
struct {
   unsigned int bit0:1;
   unsigned int ubyte:31;
} sdata;

void foo() {
  sdata.ubyte++;
}

into this:

foo:
        add DWORD PTR [sdata], 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [sdata]
        mov %ECX, %EAX
        add %ECX, 2
        and %ECX, -2
        and %EAX, 1
        or %EAX, %ECX
        mov DWORD PTR [sdata], %EAX
        ret

llvm-svn: 23376
 2005-09-18 03:42:07 +00:00
Chris Lattner
c6c62e7864 new testcase 
llvm-svn: 23375
 2005-09-18 03:39:02 +00:00
Chris Lattner
45d4ddd903 Implement hook for ppc 
llvm-svn: 23374
 2005-09-17 01:03:26 +00:00
Chris Lattner
e8cb4e7356 add a new callback 
llvm-svn: 23373
 2005-09-17 01:02:45 +00:00
Nate Begeman
d733cf7e8b More DAG combining. Still need the branch instructions, and select_cc 
llvm-svn: 23371
 2005-09-16 00:54:12 +00:00
Chris Lattner
2e3569b604 Fix a minor bug, add comments 
llvm-svn: 23370
 2005-09-16 00:29:46 +00:00
Chris Lattner
4c1ec1c784 teach the type inference code how to infer types for instructions and node 
xforms.  Run type inference on result patterns, so we always have fully typed
results (and to catch errors in .td files).

llvm-svn: 23369
 2005-09-15 22:23:50 +00:00
Chris Lattner
07b63eafa1 put instructions into a map instead of a vector for quick lookup 
llvm-svn: 23368
 2005-09-15 21:57:35 +00:00
Chris Lattner
335614b54a when parsing instructions remember information about the types taken and 
returned.

llvm-svn: 23367
 2005-09-15 21:51:12 +00:00
Chris Lattner
aa57457e20 disable this for now 
llvm-svn: 23366
 2005-09-15 21:44:00 +00:00
Chris Lattner
66c08682d9 Start parsing "Pattern" nodes 
llvm-svn: 23365
 2005-09-15 21:42:00 +00:00
Chris Lattner
fe7a70834b rename a couple of methods, add structure for pattern parsing 
llvm-svn: 23364
 2005-09-15 02:38:02 +00:00
Chris Lattner
ab6886a31d Verify that xform functions only occur in logical places 
llvm-svn: 23363
 2005-09-14 23:05:13 +00:00
Chris Lattner
6f94c802a2 Promote xform fns to be explicit nodes in result patterns, and clean off 
predicates since they will have already matched at this point.

llvm-svn: 23362
 2005-09-14 23:01:59 +00:00
Chris Lattner
57cae81b5e start building the instruction dest pattern correctly. Change the xform 
functions to preserve the Record for the xform instead of making it into a
function name.

llvm-svn: 23361
 2005-09-14 22:55:26 +00:00
Chris Lattner
a6a0d51065 catch unnamed inputs 
llvm-svn: 23360
 2005-09-14 22:06:36 +00:00
Chris Lattner
f749a0ef7c check that there are no unexpected operands 
llvm-svn: 23359
 2005-09-14 21:59:34 +00:00
Chris Lattner
9c196b02fa force all instruction operands to be named. 
llvm-svn: 23358
 2005-09-14 21:13:50 +00:00
Chris Lattner
cd5eeef9ee Give all operands names 
llvm-svn: 23357
 2005-09-14 21:11:13 +00:00
Chris Lattner
54139f0b83 give all operands names 
llvm-svn: 23356
 2005-09-14 21:10:24 +00:00
Chris Lattner
c19f24f3d7 Check that operands have unique names. REJECT instructions with broken operand 
lists: only don't parse them if they are entirely missing (sparcv9).

llvm-svn: 23355
 2005-09-14 21:05:02 +00:00
Chris Lattner
3cbcb9f5d6 fix a broke range check 
llvm-svn: 23354
 2005-09-14 21:04:12 +00:00
Chris Lattner
a5ba887c02 Parse significantly more of the instruction pattern, now collecting and 
verifying information about the operands.

llvm-svn: 23353
 2005-09-14 20:53:42 +00:00
Chris Lattner
3e8d9d8d08 Fix some issues exposed by more testing. XORIS had the wrong operands 
specified.  The various *imm operands defined by PPC are really all i32,
even though the actual immediate is restricted to a smaller value in it.

llvm-svn: 23352
 2005-09-14 20:53:05 +00:00
Chris Lattner
901ddab7b1 Verify that set destinations occur first in the instruction operand list. 
llvm-svn: 23351
 2005-09-14 18:19:25 +00:00
Chris Lattner
b97354c974 Fix some bugs noticed by new checking code 
llvm-svn: 23350
 2005-09-14 18:18:39 +00:00
Chris Lattner
76f1dae1af add an accessor 
llvm-svn: 23349
 2005-09-14 18:02:53 +00:00