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619 Commits

Author SHA1 Message Date
Colin LeMahieu
249cab3915 [llvm-objdump] Print <unknown> in place of instruction text if it couldn't be disassembled. 
llvm-svn: 263793
 2016-03-18 16:26:48 +00:00
Craig Topper
fba583ca7a [X86] Make X86MCCodeEmitter::DetermineREXPrefix locate operands more like how VEX prefix handling does. 
llvm-svn: 262467
 2016-03-02 07:32:43 +00:00
Ahmed Bougacha
19da25ce7b [X86] Move an encoding test from CodeGen to MC. NFC. 
llvm-svn: 262089
 2016-02-26 23:00:03 +00:00
Craig Topper
3a6e292b6d [X86] Add test cases for r261977 and fix a grammatical error. 
llvm-svn: 261983
 2016-02-26 06:50:24 +00:00
Igor Breger
c2763588ac AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling. 
Differential Revision: http://reviews.llvm.org/D17564

llvm-svn: 261862
 2016-02-25 13:30:17 +00:00
Igor Breger
0f4267c518 AVX512F: Add assembler Intel syntax tests for knl, fix minor bugs. 
Differential Revision: http://reviews.llvm.org/D17498

llvm-svn: 261521
 2016-02-22 12:37:41 +00:00
Igor Breger
2d437b4341 AVX512: Fix scalar mem operands. 
Differential Revision: http://reviews.llvm.org/D17500

llvm-svn: 261520
 2016-02-22 11:48:27 +00:00
Hans Wennborg
a329081c88 Revert r253557 "Alternative to long nops for X86 CPUs, by Andrey Turetsky" 
Turns out the new nop sequences aren't actually nops on x86_64 (PR26554).

llvm-svn: 261365
 2016-02-19 21:26:31 +00:00
Craig Topper
bc3298f1ee [X86] Change FeatureIFMA string to 'avx512ifma'. Matches gcc and fixes PR26461. 
llvm-svn: 260069
 2016-02-08 01:23:15 +00:00
David Majnemer
4bcb5f2151 [MC] Add support for encoding CodeView variable definition ranges 
CodeView, like most other debug formats, represents the live range of a
variable so that debuggers might print them out.

They use a variety of records to represent how a particular variable
might be available (in a register, in a frame pointer, etc.) along with
a set of ranges where this debug information is relevant.

However, the format only allows us to use ranges which are limited to a
maximum of 0xF000 in size.  This means that we need to split our debug
information into chunks of 0xF000.

Because the layout of code is not known until *very* late, we must use a
new fragment to record the information we need until we can know
*exactly* what the range is.

llvm-svn: 259868
 2016-02-05 01:55:49 +00:00
Derek Schuff
c9579c25d0 [MC] Enable eip-relative addressing on x86-64 for X32 ABI 
Summary:
Enables eip-based addressing, e.g.,

lea    constant(%eip), %rax
lea    constant(%eip), %eax

in MC, (used for the x32 ABI). EIP-base addressing is also valid in x86_64,
it is left enabled for that architecture as well.

Patch by João Porto

Differential Revision: http://reviews.llvm.org/D16581

llvm-svn: 259528
 2016-02-02 17:20:04 +00:00
Asaf Badouh
7d5bdf84bb [X86][AVX512VBMI] add encoding and intrinsics for Multishift 
Differential Revision: http://reviews.llvm.org/D16399

llvm-svn: 259363
 2016-02-01 15:48:21 +00:00
Asaf Badouh
ec3729528a [X86][IFMA] adding intrinsics and encoding for multiply and add of unsigned 52bit integer 
VPMADD52LUQ - Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators
 VPMADD52HUQ - Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators

Differential Revision: http://reviews.llvm.org/D16407

llvm-svn: 258680
 2016-01-25 11:14:24 +00:00
Michael Zuckerman
e13e338f45 [AVX512] [CMPPS ][ CMPPD ] Adding full Comparison Predicate names 
X86AsmParser.cpp is missing full comparison predicate names for CMPPD and CMPPS Instructions.
X86AsmParser.cpp defines only the short names of the Comparison predicate that you can find in the following pdf:
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf
Page 5-61 table 5-3

Differential Revision: http://reviews.llvm.org/D16518

llvm-svn: 258671
 2016-01-25 08:43:26 +00:00
Marina Yatsina
a348761e3d [X86] - Removing warning on legal cases caused by commit r258132 
There's an overloading of the "movsd" and "cmpsd" instructions, e.g. movsd can be either "Move Data from String to String" or "Move or Merge Scalar Double-Precision Floating-Point Value".
The former should produce warnings when parsing a memory operand that is not ESI/EDI, but the latter should not.

Fixed the code to produce warnings only after making sure we're dealing with the first case.

Expanded the tests of the produced warnings + fixed RUN line of the test so that it would check both stdout and stderr

Differential Revision: http://reviews.llvm.org/D16359

llvm-svn: 258393
 2016-01-21 11:37:06 +00:00
David Majnemer
7c946c0aa3 [MC, COFF] Add .reloc support for WinCOFF 
This adds rudimentary support for a few relocations that we will use for
the CodeView debug format.

llvm-svn: 258216
 2016-01-19 23:05:27 +00:00
Michael Zuckerman
553ef84e85 [AVX512] Adding VPERMT2B and VPERMI2B instruction . 
Differential Revision: http://reviews.llvm.org/D16297

llvm-svn: 258161
 2016-01-19 18:47:02 +00:00
Michael Zuckerman
71a84dc5a5 [AVX512] Adding VPERMB instruction 
Differential Revision: http://reviews.llvm.org/D16294

llvm-svn: 258144
 2016-01-19 17:07:43 +00:00
Marina Yatsina
adac739033 [X86] Add support for "xlat m8" 
According to x86 spec "xlat m8" is a legal instruction and it is equivalent to "xlatb".

Differential Revision: http://reviews.llvm.org/D15150

llvm-svn: 258135
 2016-01-19 16:35:38 +00:00
Marina Yatsina
d7dac8fde4 [X86] Adding support for missing variations of X86 string related instructions 
The following are legal according to X86 spec:
ins mem, DX
outs DX, mem
lods mem
stos mem
scas mem
cmps mem, mem
movs mem, mem

Differential Revision: http://reviews.llvm.org/D14827

llvm-svn: 258132
 2016-01-19 15:37:56 +00:00
Rafael Espindola
c8be0b633f Add a triple to the test. 
Sorry for forgetting it the first time.

llvm-svn: 257705
 2016-01-13 23:13:38 +00:00
Rafael Espindola
7f81c885ac Convert a few assert failures into proper errors. 
Fixes PR25944.

llvm-svn: 257697
 2016-01-13 22:56:57 +00:00
Craig Topper
d62ff1659a [AVX-512] Remove another extra space from the Intel syntax asm strings. 
llvm-svn: 257304
 2016-01-11 01:03:40 +00:00
Craig Topper
e6ae356ee7 [AVX-512] Remove unused Round and Itinerary from the maskable_cmp multiclasses. They weren't used and there were extra spaces in the asm string to prepare for the concatenations of the round string that wasn't ever used. 
llvm-svn: 257300
 2016-01-11 00:44:56 +00:00
Craig Topper
59a087ed05 [AVX-512] Make spacing between comma and {sae} operand consistent in asm strings. 
llvm-svn: 257299
 2016-01-11 00:44:52 +00:00
Dimitry Andric
0614f2a55e Fix several accidental DOS line endings in source files 
Summary:
There are a number of files in the tree which have been accidentally checked in with DOS line endings.  Convert these to native line endings.

There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those.

Reviewers: joerg, aaron.ballman

Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15848

llvm-svn: 256707
 2016-01-03 17:22:03 +00:00
Craig Topper
cf3121d888 [AVX512] Bring vmovq instructions names into alignment with the AVX and SSE names. Add a missing encoding to disassembler and assembler. 
I believe this also fixes a case where a 64-bit memory form that is documented as being unsupported in 32-bit mode was able to be selected there.

llvm-svn: 256483
 2015-12-28 06:11:42 +00:00
Asaf Badouh
593a27ca5c [X86][PKU] Add {RD,WR}PKRU encoding 
Differential Revision: http://reviews.llvm.org/D15711

llvm-svn: 256366
 2015-12-24 08:25:00 +00:00
Michael Zuckerman
4ee96732fb I Added a triple flag for x86-evenDirective test. 
Continue of rL255461

Differential Revision: http://reviews.llvm.org/D15413

llvm-svn: 255469
 2015-12-13 21:12:33 +00:00
Michael Zuckerman
8fdb077443 [X86][inline asm] support even directive 
The .even directive aligns content to an evan-numbered address.

In at&t syntax .even 
In Microsoft syntax even (without the dot).

Differential Revision: http://reviews.llvm.org/D15413

llvm-svn: 255462
 2015-12-13 17:07:23 +00:00
Tim Northover
db905d06b1 X86: produce more friendly errors during MachO relocation handling 
llvm-svn: 255036
 2015-12-08 18:31:35 +00:00
Michael Zuckerman
f5eedb135a dding test for fnstsw 
continue of Wrong FNSTSW size operator
url: http://reviews.llvm.org/D14953


Differential Revision: http://reviews.llvm.org/D15155

llvm-svn: 255007
 2015-12-08 12:00:24 +00:00
Marina Yatsina
905f6d3542 [X86] Adding support for FWORD type for MS inline asm 
Adding support for FWORD type for MS inline asm.

Differential Revision: http://reviews.llvm.org/D15268

llvm-svn: 254904
 2015-12-07 13:09:20 +00:00
Marina Yatsina
688b8a80f8 [X86] Add support for loopz, loopnz for Intel syntax 
According to x86 spec, loopz and loopnz should be supported for Intel syntax, where loopz is equivalent to loope and loopnz is equivalent to loopne.

Differential Revision: http://reviews.llvm.org/D15148

llvm-svn: 254877
 2015-12-06 15:31:47 +00:00
Asaf Badouh
903869d4c1 [X86][AVX512] add vmovss/sd missing encoding 
Differential Revision: http://reviews.llvm.org/D14701

llvm-svn: 254875
 2015-12-06 13:26:56 +00:00
Marina Yatsina
477847f6ac [X86] MS inline asm: produce error when encountering "<type> ptr <reg name>" 
Currently "<type> ptr <reg name>" treated as <reg name> in MS inline asm, ignoring the "<type> ptr" completely and possibly ignoring the intention of the user.
Fixed llvm to produce an error when encountering "<type> ptr <reg name>" operands.

For example: andpd xmm1,xmmword ptr xmm1 --> andpd xmm1, xmm1 
though andpd has 2 possible matching formats - andpd xmm, xmm/m128

Patch by: ziv.izhar@intel.com
Differential Revision: http://reviews.llvm.org/D14607

llvm-svn: 254607
 2015-12-03 12:17:03 +00:00
Marina Yatsina
611461b210 [X86] Add support for fcomip, fucomip for Intel syntax 
According to x86 spec, fcomip and fucomip should be supported for Intel syntax.

Differential Revision: http://reviews.llvm.org/D15104

llvm-svn: 254595
 2015-12-03 08:55:33 +00:00
Asaf Badouh
d6d08d5567 [X86][AVX512] add comi with Sae 
add builtin_ia32_vcomisd and builtin_ia32_vcomisd

Differential Revision: http://reviews.llvm.org/D14331

llvm-svn: 254493
 2015-12-02 08:17:51 +00:00
Igor Breger
31205fdf6a AVX512:Implemented encoding for the vmovq.s instruction. 
Differential Revision: http://reviews.llvm.org/D14810

llvm-svn: 254248
 2015-11-29 07:41:26 +00:00
Alexey Bataev
3304453808 Alternative to long nops for X86 CPUs, by Andrey Turetsky 
Make X86AsmBackend generate smarter nops instead of a bunch of 0x90 for code alignment for CPUs which don't support long nop instructions.
Differential Revision: http://reviews.llvm.org/D14178

llvm-svn: 253557
 2015-11-19 11:44:35 +00:00
Igor Breger
0a68600909 AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14702

llvm-svn: 253548
 2015-11-19 08:26:56 +00:00
Igor Breger
fb07c48ef1 AVX512: Implemented encoding for the vmovss.s and vmovsd.s instructions. 
Differential Revision: http://reviews.llvm.org/D14771

llvm-svn: 253547
 2015-11-19 07:58:33 +00:00
Igor Breger
8a3c708d1f AVX512: Implemented encoding for the follow instructions. 
vmovapd.s, vmovaps.s, vmovdqa32.s, vmovdqa64.s, vmovdqu16.s, vmovdqu32.s, vmovdqu64.s, vmovdqu8.s, vmovupd.s, vmovups.s

Differential Revision: http://reviews.llvm.org/D14768

llvm-svn: 253546
 2015-11-19 07:43:43 +00:00
Igor Breger
d09bcb79bc AVX512: Implemented encoding for vpextrw.s instruction. 
Differential Revision: http://reviews.llvm.org/D14766

llvm-svn: 253447
 2015-11-18 08:46:16 +00:00
Igor Breger
06ae954df6 AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14322

llvm-svn: 253185
 2015-11-16 07:22:00 +00:00
Igor Breger
02e6595c76 Revert r253160. 
It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON.

llvm-svn: 253163
 2015-11-15 12:19:11 +00:00
Igor Breger
3ec0d86d6a AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14322

llvm-svn: 253160
 2015-11-15 07:23:13 +00:00
Michael Zuckerman
b36f5b984e [x86] translating "fp" (floating point) instructions from {fadd,fdiv,fmul,fsub,fsubr,fdivr} to {faddp,fdivp,fmulp,fsubp,fsubrp,fdivrp} 
LLVM Missing the following instructions: fadd\fdiv\fmul\fsub\fsubr\fdivr.
GAS and MS supporting this instruction and lowering them in to a faddp\fdivp\fmulp\fsubp\fsubrp\fdivrp instructions.

Differential Revision: http://reviews.llvm.org/D14217

llvm-svn: 252908
 2015-11-12 16:58:51 +00:00
Douglas Katzman
f853537965 Visibly fail if attempting to encode register AH,BH,CH,DH in a REX-prefixed instruction. 
Differential Revision: http://reviews.llvm.org/D13316
Fixes PR25003

llvm-svn: 252743
 2015-11-11 15:51:16 +00:00
Igor Breger
bfb07ae48a AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD instructions. 
Differential Revision: http://reviews.llvm.org/D14492

llvm-svn: 252592
 2015-11-10 07:09:07 +00:00
Asaf Badouh
f3f551dd7e revert rev. 252153 due to build failure on ubuntu 
[X86][AVX512] add comi with Sae

llvm-svn: 252154
 2015-11-05 08:55:54 +00:00
Asaf Badouh
c9c8bfa4c4 [X86][AVX512] add comi with Sae 
add builtin_ia32_vcomisd and builtin_ia32_vcomisd

Differential Revision: http://reviews.llvm.org/D14331

llvm-svn: 252153
 2015-11-05 08:45:06 +00:00
Asaf Badouh
e9eadcdf13 [X86][AVX512] small bugfix in VPBROADCASTM 
VPBROADCASTMW2D and VPBROADCASTMB2Q

Differential Revision: http://reviews.llvm.org/D14335

llvm-svn: 252151
 2015-11-05 08:08:21 +00:00
Rafael Espindola
1d7efb8a20 Fix pr24832. 
It is pretty simple now that the yak is shaved.

llvm-svn: 252105
 2015-11-05 00:10:08 +00:00
Igor Breger
207c14b67f AVX512: add encoding tests for vmovq/d instructions. 
llvm-svn: 251903
 2015-11-03 07:30:17 +00:00
Igor Breger
dd070c17bb AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and VBROADCASTF32x2 instructions. 
Differential Revision: http://reviews.llvm.org/D14216

llvm-svn: 251781
 2015-11-02 07:39:36 +00:00
Asaf Badouh
2110df5fda [X86][AVX512] [X86][AVX512] add convert float to half 
convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem).

Differential Revision: http://reviews.llvm.org/D14113

llvm-svn: 251409
 2015-10-27 15:37:17 +00:00
David Majnemer
0e608b0bdb [MC] Add support for GNU as-compatible binary operator precedence 
GNU as and Darwin give the various binary operators different
precedence.  LLVM's MC supported the Darwin semantics but not the GNU
semantics.

This fixes PR25311.

llvm-svn: 251271
 2015-10-26 03:15:34 +00:00
Asaf Badouh
99f2354837 [X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versions 
Differential Revision: http://reviews.llvm.org/D13945

llvm-svn: 251018
 2015-10-22 14:01:16 +00:00
Craig Topper
dcce633156 [X86] Add AMD mwaitx, monitorx, and clzero instructions to the assembly parser and disassembler. 
llvm-svn: 250911
 2015-10-21 17:26:45 +00:00
Igor Breger
c385abd09d AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions. 
Differential Revision: http://reviews.llvm.org/D13884

llvm-svn: 250819
 2015-10-20 11:56:42 +00:00
Asaf Badouh
381b11d5f2 [X86][AVX512DQ] add scalar fpclass 
Differential Revision: http://reviews.llvm.org/D13769

llvm-svn: 250650
 2015-10-18 11:04:38 +00:00
Igor Breger
6e29702ee8 AVX512: Implemented encoding and intrinsics for vpternlogd/q. 
Differential Revision: http://reviews.llvm.org/D13768

llvm-svn: 250396
 2015-10-15 12:33:24 +00:00
Craig Topper
18c728de25 [X86] Change the immediate for IN/OUT instructions to u8imm so the assembly parser will check the size. 
llvm-svn: 250012
 2015-10-12 04:17:55 +00:00
Craig Topper
7a2aafba5d [X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior. 
This also fixes a bug where negative immediates below -128 were not being reported as errors.

llvm-svn: 249989
 2015-10-11 18:27:24 +00:00
Igor Breger
63cd1bda1b AVX512: vpextrb/w/d/q and vpinsrb/w/d/q implementation. 
This instructions doesn't have intrincis.
Added tests for lowering and encoding.

Differential Revision: http://reviews.llvm.org/D12317

llvm-svn: 249688
 2015-10-08 12:55:01 +00:00
Igor Breger
495e2a8625 AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG as W0 and not W1, like all other instruction have been implemented. 
Add encoding tests.

Differential Revision: http://reviews.llvm.org/D13471

llvm-svn: 249521
 2015-10-07 06:31:18 +00:00
Igor Breger
38dd6d8710 AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12690

llvm-svn: 249261
 2015-10-04 07:20:41 +00:00
Asaf Badouh
8011b4b495 [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP 
Differential Revision: http://reviews.llvm.org/D12524

llvm-svn: 248147
 2015-09-21 10:23:53 +00:00
Igor Breger
a833017e0d AVX512: Implemented encoding and intrinsics for vcmpss/sd. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12593

llvm-svn: 248121
 2015-09-20 15:15:10 +00:00
Asaf Badouh
4ce11a0a36 [X86][AVX512] extend support in Scalar conversion 
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics

Differential Revision: http://reviews.llvm.org/D12665

llvm-svn: 248117
 2015-09-20 14:31:19 +00:00
Igor Breger
6c78cd17ac AVX512: vsqrtss/sd encoding and intrinsics implementation. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12102

llvm-svn: 248116
 2015-09-20 09:13:41 +00:00
Asaf Badouh
981ab82bef [X86][AVX512DQ] Add fpclass instruction 
Differential Revision: http://reviews.llvm.org/D12931

llvm-svn: 248115
 2015-09-20 08:46:07 +00:00
Igor Breger
43e0d98a01 AVX512: Implement instructions encoding, lowering and intrinsics 
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.

Differential Revision: http://reviews.llvm.org/D11893

llvm-svn: 248111
 2015-09-20 06:52:42 +00:00
Igor Breger
eeecfc6724 AVX512: Implemented encoding and intrinsics for 
vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

llvm-svn: 247276
 2015-09-10 12:54:54 +00:00
Renato Golin
32a92f6d16 Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding." 
This reverts commit r247149, as it was breaking numerous buildbots of varied architectures.

llvm-svn: 247177
 2015-09-09 19:44:40 +00:00
Igor Breger
1a3ef530c1 AVX512: Implemented encoding and intrinsics for 
vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

llvm-svn: 247149
 2015-09-09 14:35:09 +00:00
Igor Breger
2caf00654a AVX512: kunpck encoding implementation 
Added tests for encoding.

Differential Revision: http://reviews.llvm.org/D12061

llvm-svn: 247010
 2015-09-08 13:10:00 +00:00
Igor Breger
63fab329a2 AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, vpconflictq, vpconflictd 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11931

llvm-svn: 246750
 2015-09-03 09:05:31 +00:00
Asaf Badouh
70ff5c87a7 [X86][AVX512VLBW] add support in byte shift and SAD 
add byte shift left/right
add SAD - compute sum of absolute differences

Differential Revision: http://reviews.llvm.org/D12479

llvm-svn: 246654
 2015-09-02 14:21:54 +00:00
Igor Breger
8e7d569bab AVX512: Implemented encoding and intrinsics for VGETMANTPD/S , VGETMANTSD/S instructions 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11593

llvm-svn: 246642
 2015-09-02 11:18:55 +00:00
Igor Breger
dc46fb3351 AVX512: Implemented encoding and intrinsics for vshufps/d. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11709

llvm-svn: 246640
 2015-09-02 10:50:58 +00:00
Igor Breger
e7da3698f2 AVX512: ktest implemantation 
Added tests for encoding.

Differential Revision: http://reviews.llvm.org/D11979

llvm-svn: 246439
 2015-08-31 13:30:19 +00:00
Igor Breger
2ff3c16585 AVX512: Implemented encoding and intrinsics for vdbpsadbw 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12491

llvm-svn: 246436
 2015-08-31 13:09:30 +00:00
Igor Breger
d931ce02d4 AVX512: kadd implementation 
Added tests for encoding.

Differential Revision: http://reviews.llvm.org/D11973

llvm-svn: 246432
 2015-08-31 11:50:23 +00:00
Igor Breger
0b3d48f3ef AVX512: Add encoding tests for vscatter instructions 
Differential Revision: http://reviews.llvm.org/D11941

llvm-svn: 246431
 2015-08-31 11:33:50 +00:00
Igor Breger
c6e71f91ab AVX512: Implemented encoding and intrinsics for vpalignr 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12270

llvm-svn: 246428
 2015-08-31 11:14:02 +00:00
Michael Zuckerman
ae040817a7 [X86] Add support for mmword memory operand size for Intel-syntax x86 assembly 
Differential Revision: http://reviews.llvm.org/D12151

llvm-svn: 245835
 2015-08-24 10:26:54 +00:00
Rafael Espindola
f1083e7ba6 Fix symbol value computation when part of the expression is weak. 
This matches the behaviour of the gnu assembler and is part of
fixing pr24486.

llvm-svn: 245576
 2015-08-20 16:18:30 +00:00
Marina Yatsina
4f67f6d0b5 [X86] Fix FBLD and FBSTP 
FBLD and FBSTP should receive TBYTE because it is defined as
FBLD m80
FBSTP m80

Differential Revision: http://reviews.llvm.org/D11748

llvm-svn: 245553
 2015-08-20 11:51:24 +00:00
Marina Yatsina
668150fc2f [X86] Fix bug in COMISD and COMISS definition in td files 
COMISD should receive QWORD because it is defined as
 (V)COMISD xmm1, xmm2/m64

COMISS should receive DWORD because it is defined as
 (V)COMISS xmm1, xmm2/m32

Differential Revision: http://reviews.llvm.org/D11712

llvm-svn: 245551
 2015-08-20 11:21:36 +00:00
Davide Italiano
658151efe6 [MC] Convert the last test using macho-dump under X86/ to llvm-readobj. 
llvm-svn: 244732
 2015-08-12 10:36:16 +00:00
Marina Yatsina
a28fbe6a96 [X86] Add SAL mnemonics for Intel syntax 
SAL and SHL instructions perform the same operation

Differential Revision: http://reviews.llvm.org/D11882

llvm-svn: 244588
 2015-08-11 12:05:06 +00:00
Marina Yatsina
fc986c89c0 [X86] Fix REPE, REPZ, REPNZ for intel syntax 
REPE, REPZ, REPNZ, REPNE should have mnemonics for Intel syntax as well.
Currently using these instructions causes compilation errors for Intel syntax.

Differential Revision: http://reviews.llvm.org/D11794

llvm-svn: 244584
 2015-08-11 11:28:10 +00:00
Marina Yatsina
d8e14460d5 [X86] Fix imul alias for intel syntax 
The "imul reg, imm" alias is not defined for intel syntax. 
In intel syntax there is no w/l/q suffix for the imul instruction.

Differential Revision: http://reviews.llvm.org/D11887

llvm-svn: 244582
 2015-08-11 10:43:04 +00:00
Duncan P. N. Exon Smith
87c77233df DI: Disallow uniquable DICompileUnits 
Since r241097, `DIBuilder` has only created distinct `DICompileUnit`s.
The backend is liable to start relying on that (if it hasn't already),
so make uniquable `DICompileUnit`s illegal and automatically upgrade old
bitcode.  This is a nice cleanup, since we can remove an unnecessary
`DenseSet` (and the associated uniquing info) from `LLVMContextImpl`.

Almost all the testcases were updated with this script:

    git grep -e '= !DICompileUnit' -l -- test |
    grep -v test/Bitcode |
    xargs sed -i '' -e 's,= !DICompileUnit,= distinct !DICompileUnit,'

I imagine something similar should work for out-of-tree testcases.

llvm-svn: 243885
 2015-08-03 17:26:41 +00:00
Igor Breger
b86cbff9ff AVX512: Add encoding tests to vptestnm instructions 
Differential Revision: http://reviews.llvm.org/D11521

llvm-svn: 243391
 2015-07-28 07:00:00 +00:00
Igor Breger
28223d1ba3 AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructions 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11528

llvm-svn: 243390
 2015-07-28 06:53:28 +00:00
Igor Breger
255a11f9b8 Implemented encoding and intrinsics of the following instructions 
vunpckhps/pd, vunpcklps/pd, 
  vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11509

llvm-svn: 243246
 2015-07-26 14:41:44 +00:00
Igor Breger
7ea6c4cce1 AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation 
Added tests for DAG lowering ,encoding and intrinsic

Differential Revision: http://reviews.llvm.org/D11218

llvm-svn: 243122
 2015-07-24 17:24:15 +00:00
Michael Kuperstein
197cefcc3e [X86] Fix order of operands for ins and outs instructions when parsing intel syntax 
Patch by: marina.yatsina@intel.com
Differential Revision: http://reviews.llvm.org/D11337

llvm-svn: 243001
 2015-07-23 10:23:48 +00:00
Chandler Carruth
3b9bc26920 Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..." 
This commit broke the build. Numerous build bots broken, and it was
blocking my progress so reverting.

It should be trivial to reproduce -- enable the BPF backend and it
should fail when running llvm-tblgen.

llvm-svn: 242992
 2015-07-23 08:03:44 +00:00
Igor Breger
8ded9931fe AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation 
Added tests for DAG lowering ,encoding and intrinsic

Differential Revision: http://reviews.llvm.org/D11218

llvm-svn: 242990
 2015-07-23 07:39:21 +00:00
Asaf Badouh
7feb9eaba0 [X86][AVX512] add reduce/range/scalef/rndScale 
include encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D11222

llvm-svn: 242896
 2015-07-22 12:00:43 +00:00
Michael Kuperstein
6cb752cf86 Fix test from r242886 to use the right triple. 
llvm-svn: 242889
 2015-07-22 11:19:22 +00:00
Michael Kuperstein
80699ec16e [X86] Add .intel_syntax noprefix directive to intel-syntax x86 asm output 
Patch by: michael.zuckerman@intel.com
Differential Revision: http://reviews.llvm.org/D11223

llvm-svn: 242886
 2015-07-22 10:49:44 +00:00
Igor Breger
5441f451cc AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11351

llvm-svn: 242761
 2015-07-21 07:11:28 +00:00
Michael Kuperstein
3563778983 [X86] Add support for tbyte memory operand size for Intel-syntax x86 assembly 
Differential Revision: http://reviews.llvm.org/D11257
Patch by: marina.yatsina@intel.com

llvm-svn: 242639
 2015-07-19 11:03:08 +00:00
Elena Demikhovsky
618bae6f38 AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types. 
In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch.
I temporary removed the old intrinsics test (just to split this patch).
Half types are not covered here.

Differential Revision: http://reviews.llvm.org/D11134

llvm-svn: 242023
 2015-07-13 13:26:20 +00:00
David Majnemer
40f539becd [llvm-objdump] Require that jump targets shown in -d are functions 
Don't let the disassembler pick call <.text> if a function happens to
live at the start of the section by only using function symbols.

llvm-svn: 241830
 2015-07-09 18:11:40 +00:00
David Majnemer
9584e54586 [llvm-objdump] Print the call target next to the instruction 
GNU binutils provides this behavior.  objdump -r doesn't really help
when you aren't dealing with relocation object files.

llvm-svn: 241631
 2015-07-07 22:06:59 +00:00
Asaf Badouh
a51b8d0d5b [X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale 
pmulhrsw

review:
http://reviews.llvm.org/D10948

llvm-svn: 241443
 2015-07-06 14:03:40 +00:00
Asaf Badouh
7e53a288e3 [x86][AVX512] add Multiply High Op 
include encoding and intrinsics tests.

review
http://reviews.llvm.org/D10896

llvm-svn: 241406
 2015-07-05 12:23:20 +00:00
Craig Topper
3faa86f8f9 [X86] Add proper 64-bit mode checks to jrcxz and jcxz. 
llvm-svn: 241381
 2015-07-04 00:01:07 +00:00
Igor Breger
cdff3524c0 AVX-512: Implemented missing encoding for FMA scalar instructions 
Added tests for encoding

Differential Revision: http://reviews.llvm.org/D10865

llvm-svn: 241159
 2015-07-01 13:24:28 +00:00
Elena Demikhovsky
12bde41e5a AVX-512: all forms of SCATTER instruction on SKX, 
encoding, intrinsics and tests.

llvm-svn: 240936
 2015-06-29 12:14:24 +00:00
Igor Breger
7ca2ee2eb1 AVX-512: Implemented missing encoding and intrinsics for FMA instructions 
Added tests for DAG lowering ,encoding and intrinsics

Differential Revision: http://reviews.llvm.org/D10796

llvm-svn: 240926
 2015-06-29 09:10:00 +00:00
Asaf Badouh
732e3b5425 [x86][AVX512] 
Add vscalef support
include encoding and intrinsics


review:
http://reviews.llvm.org/D10730

llvm-svn: 240906
 2015-06-28 14:30:39 +00:00
Elena Demikhovsky
02169f53d0 AVX-512: Added all SKX forms of GATHER instructions. 
Added intrinsics.
Added encoding and tests.

llvm-svn: 240905
 2015-06-28 10:53:29 +00:00
Petr Hosek
7d5572358c [MC] Ensure that pending labels are flushed when -mc-relax-all flag is used 
Summary:
The current implementation doesn't always flush all pending labels
beforeemitting data which can result in an incorrectly placed labels in
case when when instruction bundling is enabled and -mc-relax-all flag is
being used. To address this issue, we always flush pending labels before
emitting data.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10325

llvm-svn: 240870
 2015-06-27 01:54:17 +00:00
Petr Hosek
0b66377b09 [MC] Align fragments when -mc-relax-all flag is used 
Summary:
Ensure that fragments are bundle aligned when instruction bundling
is enabled and the -mc-relax-all flag is set. This is implicitly
assumed by the bundle padding implementation but this assumption
does not hold when custom alignment is being used.

The change was tested by running PNaCl toolchain trybots with
-mc-relax-all flag set.

Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063

Test Plan: Regression test attached

Reviewers: mseaborn

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10044

llvm-svn: 240869
 2015-06-27 01:49:53 +00:00
Rafael Espindola
393725d952 Add a test for a recent regression. 
llvm-svn: 240656
 2015-06-25 16:16:08 +00:00
Elena Demikhovsky
1df83908be AVX-512: Added all forms of VPABS instruction 
Added all intrinsics, tests for encoding, tests for intrinsics.

llvm-svn: 240386
 2015-06-23 08:19:46 +00:00
Sanjoy Das
bea61317e9 [FaultMaps] Add a parser for the __llvm__faultmaps section. 
Summary:
The parser is exercised by llvm-objdump using -print-fault-maps.  As is
probably obvious, the code itself was "heavily inspired" by
http://reviews.llvm.org/D10434.

Reviewers: reames, atrick, JosephTremoulet

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10491

llvm-svn: 240304
 2015-06-22 18:03:02 +00:00
Elena Demikhovsky
0d6489273b AVX-512: added VPSHUFB instruction - all SKX forms 
Added intrinsics and encoding tests.

llvm-svn: 240277
 2015-06-22 13:00:42 +00:00
Elena Demikhovsky
833648a31f AVX-512: All forms of VCOPMRESS VEXPAND instructions, 
encoding tests.

llvm-svn: 240272
 2015-06-22 11:16:30 +00:00
Asaf Badouh
6e78caf9ff [AVX512] 
add instructions: VPAVGB and VPAVGW


review
http://reviews.llvm.org/D10504

llvm-svn: 240012
 2015-06-18 12:30:53 +00:00
Elena Demikhovsky
e3fe4bf53e AVX-512: (fixed) Added encoding of all forms of VPERMT2W/D/Q/PS/PD and VPERMI2W/D/Q/PS/PD. 
Intrinsics and tests for them are comming in the next patch.

llvm-svn: 240003
 2015-06-18 08:56:19 +00:00
Elena Demikhovsky
dc7dd8572b reverted 239999 due to test failures 
llvm-svn: 240001
 2015-06-18 08:06:49 +00:00
Elena Demikhovsky
f5554ec461 AVX-512: Added encoding of all forms of VPERMT2W/D/Q/PS/PD 
and VPERMI2W/D/Q/PS/PD.
Intrinsics and tests for them are comming in the next patch.

llvm-svn: 239999
 2015-06-18 07:29:40 +00:00
Michael Kuperstein
915c69271d Add support for parsing the XOR operator in Intel syntax inline assembly. 
Differential Revision: http://reviews.llvm.org/D10385
Patch by marina.yatsina@intel.com

llvm-svn: 239695
 2015-06-14 12:59:45 +00:00
Igor Breger
f163333815 AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL. 
Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D10430

llvm-svn: 239694
 2015-06-14 12:44:55 +00:00
Elena Demikhovsky
b46f844518 X86-MPX: Implemented encoding for MPX instructions. 
Added encoding tests.

llvm-svn: 239403
 2015-06-09 13:02:10 +00:00
Igor Breger
545f43a067 AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL 
Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.

Differential Revision: http://reviews.llvm.org/D10310

llvm-svn: 239300
 2015-06-08 14:03:17 +00:00
Colin LeMahieu
fb88ee51e5 [objdump] Moving PrintImmHex out of MachODump and in to llvm-objdump and setting instprinter appropriately. 
llvm-svn: 239265
 2015-06-07 21:07:17 +00:00
Igor Breger
452695b2e5 Test commit 
llvm-svn: 239019
 2015-06-04 07:23:38 +00:00
Elena Demikhovsky
2b7fd2c6ef AVX-512: added all SKX forms of VPERMW/D/Q instructions. 
Added all forms of VPERMPS/PD instrcuctions.
Added encoding tests.

llvm-svn: 239016
 2015-06-04 07:07:13 +00:00
Asaf Badouh
08f13fa0ba re-apply 238809 
AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
CR:
http://reviews.llvm.org/D9991

llvm-svn: 238923
 2015-06-03 13:41:48 +00:00
Elena Demikhovsky
13b85a4aa6 AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions for SKX and KNL. 
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)

llvm-svn: 238917
 2015-06-03 10:56:40 +00:00
Elena Demikhovsky
c14282d277 AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented DAG lowering for all these forms. 
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)

llvm-svn: 238834
 2015-06-02 14:12:54 +00:00
Elena Demikhovsky
9402ebb636 AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL 
Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)

llvm-svn: 238811
 2015-06-02 08:28:57 +00:00
Asaf Badouh
f8387bd5f5 revert 238809 
llvm-svn: 238810
 2015-06-02 07:45:19 +00:00
Asaf Badouh
9a55f1d0aa AVX-512: Implemented GETEXP instruction for KNL and SKX 
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.

llvm-svn: 238809
 2015-06-02 07:18:14 +00:00
Asaf Badouh
db0710de25 First commit test. 
llvm-svn: 238745
 2015-06-01 13:56:00 +00:00
Elena Demikhovsky
9e9a44e5bd AVX-512: Implemented VRANGEPD and VRANGEPD instructions for SKX. 
Implemented DAG lowering for all these forms.
Added tests for encoding.

By Igor Breger (igor.breger@intel.com)

llvm-svn: 238738
 2015-06-01 11:05:34 +00:00
Elena Demikhovsky
12406985ca AVX-512: added all forms of VPSHUFD and VPSHUFHW, VPSHUFLW 
including encodings.

llvm-svn: 238729
 2015-06-01 07:17:23 +00:00
Elena Demikhovsky
9db95755e6 AVX-512: Implemented VFIXUPIMMPD and VFIXUPIMMPS instructions for KNL and SKX 
Implemented DAG lowering for all these forms.
Added tests for encoding.

by Igor Breger (igor.breger@intel.com)

llvm-svn: 238728
 2015-06-01 06:50:49 +00:00
Ahmed Bougacha
e255a8b38a [TableGen][AsmMatcherEmitter] Only parse isolated tokens as registers. 
Fixes PR23455, where, when TableGen generates the matcher from the
AsmString, it splits "cmp${cc}ss" into tokens, and the "ss" suffix
is recognized as the SS register.

I can't think of a situation where that's a feature, not a bug, hence:
when a token is "isolated", i.e., it is followed and preceded by
separators, it shouldn't be parsed as a register.

Differential Revision: http://reviews.llvm.org/D9844

llvm-svn: 238536
 2015-05-29 01:03:37 +00:00
Elena Demikhovsky
51096c6536 AVX-512: Implemented all forms of sign-extend and zero-extend instructions for KNL and SKX 
Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.

By Igor Breger (igor.breger@intel.com)

llvm-svn: 238301
 2015-05-27 08:15:19 +00:00
Elena Demikhovsky
7d3b86db52 AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other instructions from this set 
Added encoding tests.

llvm-svn: 237557
 2015-05-18 06:42:57 +00:00