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38690 Commits

Author SHA1 Message Date
Daniel Dunbar
ee525943d8 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
llvm-svn: 104452
 2010-05-22 21:02:29 +00:00
Daniel Dunbar
7c60f7caa2 MC/X86: Add alias for setz, setnz, jz, jnz. 
llvm-svn: 104435
 2010-05-22 06:37:33 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977. 
llvm-svn: 104421
 2010-05-22 01:47:14 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Bob Wilson
b8ebb375b6 Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by 
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415
 2010-05-22 00:23:12 +00:00
Eric Christopher
165bcdf8a8 Add full bss data support for darwin tls variables. 
llvm-svn: 104414
 2010-05-22 00:10:22 +00:00
Devang Patel
e611375617 Collect variable information during endFunction() instead of beginFunction(). 
llvm-svn: 104412
 2010-05-22 00:04:14 +00:00
Bob Wilson
3994f42952 Clean up extra whitespace. 
llvm-svn: 104410
 2010-05-21 23:53:55 +00:00
Eric Christopher
8f296fd844 Make this LookAheadLimit, not the uninitialized LookAheadLeft. 
Evan please verify!

llvm-svn: 104408
 2010-05-21 23:40:03 +00:00
Chris Lattner
d5c391bba6 add a note 
llvm-svn: 104404
 2010-05-21 23:16:21 +00:00
Eric Christopher
d250f449cb Expand on comment. 
llvm-svn: 104396
 2010-05-21 23:03:53 +00:00
Kevin Enderby
1e4a4f5899 Added retl for 32-bit x86 and added retq for 64-bit x86. 
llvm-svn: 104394
 2010-05-21 23:01:38 +00:00
Evan Cheng
6a0784954a Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs. 
llvm-svn: 104385
 2010-05-21 21:22:19 +00:00
Eric Christopher
5fc9256574 Fix section attribute name. 
llvm-svn: 104381
 2010-05-21 21:08:52 +00:00
Bob Wilson
586811b244 Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
 2010-05-21 21:05:32 +00:00
Evan Cheng
3c850aecf6 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
 2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
0f1087b284 Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction 
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372
 2010-05-21 20:02:01 +00:00
Devang Patel
e8f686625e Simplify 
llvm-svn: 104338
 2010-05-21 18:49:09 +00:00
Dale Johannesen
787ace240c Previous commit message should refer to 104308. 
llvm-svn: 104337
 2010-05-21 18:44:47 +00:00
Dale Johannesen
38109a0b04 Fix two bugs in 104348: 
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.

llvm-svn: 104336
 2010-05-21 18:40:15 +00:00
Chris Lattner
4c14d2c4a4 now that fp reg kill insertion stuff happens as a separate 
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.

llvm-svn: 104333
 2010-05-21 18:17:54 +00:00
Chris Lattner
1e1fb36df4 Use less evil form of switch stmt. 
llvm-svn: 104331
 2010-05-21 18:02:42 +00:00
Chris Lattner
8c562574eb use continue to reduce nesting. 
llvm-svn: 104330
 2010-05-21 18:01:24 +00:00
Chris Lattner
2077759153 pull a nested loop of this pass out to its own function, 
eliminating the gymnastics around the ContainsFPCode var.

llvm-svn: 104328
 2010-05-21 17:57:03 +00:00
Chris Lattner
91ffa7a5bf modernize this pass a bit, fit in 80 columns. 
llvm-svn: 104326
 2010-05-21 17:49:07 +00:00
Chris Lattner
1794093960 constify accessor. 
llvm-svn: 104325
 2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
a3cca88b41 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." 
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
 2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
edf8136011 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
924b84cf0f Teach VirtRegRewriter to handle spilling in instructions that have multiple 
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

llvm-svn: 104321
 2010-05-21 16:36:13 +00:00
Jakob Stoklund Olesen
6c22635216 If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
 2010-05-21 16:32:16 +00:00
Matt Fleming
5d40d53cab Currently, createMachOStreamer() is invoked directly in llvm-mc which 
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.

llvm-svn: 104318
 2010-05-21 12:54:43 +00:00
Matt Fleming
6a5cb8c84a Split out the x86_32 an x86_64 ELF backends as they handle ELF 
differently. This will make adding ELF support easier in the long run.

llvm-svn: 104317
 2010-05-21 11:39:07 +00:00
Matt Fleming
0ca99c0262 Add support for parsing the ELF .type assembler directive. 
llvm-svn: 104316
 2010-05-21 11:36:59 +00:00
Dale Johannesen
d0a5fdb32f Fix i64->f64 conversion, x86-64, -no-sse. A bit 
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.

llvm-svn: 104308
 2010-05-21 00:52:33 +00:00
Evan Cheng
6397a77e16 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
llvm-svn: 104307
 2010-05-21 00:43:17 +00:00
Evan Cheng
1faccbd51a Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid. 
llvm-svn: 104306
 2010-05-21 00:42:32 +00:00
Devang Patel
765d605934 Simplify. 
llvm-svn: 104302
 2010-05-21 00:10:20 +00:00
Daniel Dunbar
38460e2596 Fix __crashreport_info__ declaration. 
llvm-svn: 104300
 2010-05-20 23:50:19 +00:00
Evan Cheng
b5de7de4ce Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
llvm-svn: 104293
 2010-05-20 23:26:43 +00:00
Dan Gohman
3274120902 DominatorTree.getNode can return null for unreachable blocks. 
llvm-svn: 104290
 2010-05-20 22:46:54 +00:00
Dan Gohman
b841e5c433 Minor code cleanups. 
llvm-svn: 104287
 2010-05-20 22:25:20 +00:00
Mikhail Glushenkov
5ead1e50a7 Print a space after the colon. 
llvm-svn: 104279
 2010-05-20 21:11:37 +00:00
Dan Gohman
06b35689ec Make Solve check its own post-condition, to reduce clutter in the 
top-level LSRInstance logic.

llvm-svn: 104278
 2010-05-20 20:59:23 +00:00
Dan Gohman
2702e3105d Add comments. 
llvm-svn: 104276
 2010-05-20 20:52:00 +00:00
Daniel Dunbar
3a0c98ca87 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
llvm-svn: 104275
 2010-05-20 20:36:29 +00:00
Devang Patel
3d4cd812aa Rename variable. add comment. 
llvm-svn: 104274
 2010-05-20 20:35:24 +00:00
Dan Gohman
5f16e1b2cb More code cleanups. Use iterators instead of indices when indices 
aren't needed.

llvm-svn: 104273
 2010-05-20 20:33:18 +00:00
Daniel Dunbar
030b1001c0 X86: Model i64i32imm properly, as a subclass of all immediates. 
llvm-svn: 104272
 2010-05-20 20:20:39 +00:00
Daniel Dunbar
6cbde7d71e X86: Fix immediate type of FOO64i32 operations. 
llvm-svn: 104271
 2010-05-20 20:20:35 +00:00
Dan Gohman
aa116e0758 Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set 
Changed directly instead of using a return value.

Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.

llvm-svn: 104269
 2010-05-20 20:05:31 +00:00