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Commit Graph

150528 Commits

Author SHA1 Message Date
Adrian Prantl
bfedffd3b8 Add previously accidentally uncommitted testcase for r305599.
llvm-svn: 305852
2017-06-20 21:08:19 +00:00
Kevin Enderby
c4ac67070a Change llvm-objdump with Mach-O files and the -info-plist option with the
-no-leading-headers option so that it does not print the leading header.

rdar://27378808

llvm-svn: 305849
2017-06-20 21:00:25 +00:00
Anna Thomas
eee230003b [Statepoint] Add helper functions for GCRelocate and GCResult
These functions isGCRelocate and isGCResult are
similar to isStatepoint(const Value*).

llvm-svn: 305847
2017-06-20 20:54:57 +00:00
Saleem Abdulrasool
a1892fc5c5 Support: chunk writing on Linux
This is a workaround for large file writes.  It has been witnessed that
write(2) failing with EINVAL (22) due to a large value (>2G).  Thanks to
James Knight for the help with coming up with a sane test case.

llvm-svn: 305846
2017-06-20 20:51:51 +00:00
Matt Arsenault
6a83f83b14 AMDGPU: Allow vectorization of packed types
llvm-svn: 305844
2017-06-20 20:38:06 +00:00
Reid Kleckner
a69be8fb50 [codeview] Fully initialize DataSym when mapping from YAML
In the object file, the section index and relative offset are typically
zero, so make these YAML fields optional with a default.

It looks like there may be more partially initialized symbol records,
but this should fix the msan bot.

llvm-svn: 305842
2017-06-20 20:34:37 +00:00
Stanislav Mekhanoshin
38e25ffa46 [AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32
If there is an immediate operand we shall not shrink V_SUBB_U32
and V_ADDC_U32, it does not fit e32 encoding.

Differential Revison: https://reviews.llvm.org/D34291

llvm-svn: 305840
2017-06-20 20:33:44 +00:00
Michael Gottesman
be2e357fd1 [cmake] Add support for using the standalone leaks sanitizer with LLVM.
This commit causes LLVM_USE_SANITIZER to now accept the "Leaks" option. This
will cause cmake to pass in -fsanitize=leak in all of the appropriate places.

I am making this change so that I can setup a linux bot that only detects
leaks.

llvm-svn: 305839
2017-06-20 20:28:07 +00:00
Matt Arsenault
8ecc22a003 AMDGPU: Start adding global_* instructions
llvm-svn: 305838
2017-06-20 19:54:14 +00:00
Aditya Nandakumar
88f603bd96 [GISel]: NFC. Add comment to G_FMA opcode as requested in rL305824
llvm-svn: 305837
2017-06-20 19:52:29 +00:00
Aditya Nandakumar
48c7ec9aa0 [GISel]: Add G_FMA opcode for fused multiply adds
https://reviews.llvm.org/D34372

Reviewed by dsanders

llvm-svn: 305824
2017-06-20 19:25:23 +00:00
Matt Arsenault
0600162b6b AMDGPU: Do operand folding in program order
Before it was possible to partially fold use instructions
before the defs. After the xor is folded into a copy, the same
mov can end up in the fold list twice, so on the second attempt
it will fail expecting to see a register to fold.

llvm-svn: 305821
2017-06-20 18:56:32 +00:00
Zachary Turner
c6fbceb28e [PDB] Don't write uninitialized bytes to a PDB file.
There were certain fields that we didn't know how to write, as
well as various padding bytes that we would ignore.  This leads
to garbage data in the PDB.  While not strictly necessary, we
should initialize these bytes to something meaningful, as it
makes for easier binary comparison between PDBs.

llvm-svn: 305819
2017-06-20 18:50:55 +00:00
Zachary Turner
bafdd700f2 Remove diff pedantic mode.
llvm-svn: 305818
2017-06-20 18:50:30 +00:00
Matthias Braun
4512fd3488 RegisterScavenging: Followup to r305625
This does some improvements/cleanup to the recently introduced
scavengeRegisterBackwards() functionality:

- Rewrite findSurvivorBackwards algorithm to use the existing
  LiveRegUnit::accumulateBackward() code. This also avoids the Available
  and Candidates bitset and just need 1 LiveRegUnit instance
  (= 1 bitset).
- Pick registers in allocation order instead of register number order.

llvm-svn: 305817
2017-06-20 18:43:14 +00:00
Matt Arsenault
82195867aa AMDGPU: Preserve undef when folding register operands
If the source was a copy of an undef register, this would
produce a read of an undefined register which is a verifier
error.

llvm-svn: 305816
2017-06-20 18:41:31 +00:00
Stanislav Mekhanoshin
b3cc641434 [AMDGPU] Eliminate SGPR to VGPR copy when possible
SGPRs are generally cheaper, so try to use them over VGPRs.

Differential Revision: https://reviews.llvm.org/D34130

llvm-svn: 305815
2017-06-20 18:32:42 +00:00
Matt Arsenault
dcca3a04d1 AMDGPU: Fix crash with undef vreg input operand
llvm-svn: 305814
2017-06-20 18:28:02 +00:00
Hiroshi Inoue
aa8d2c3186 [PowerPC] fix trivial typos in comment, NFC
llvm-svn: 305813
2017-06-20 17:53:33 +00:00
Simon Pilgrim
87025c75e2 [CostModel][X86] Add scalar arithmetic cost tests
llvm-svn: 305810
2017-06-20 17:10:27 +00:00
Simon Pilgrim
f41727e6d0 [CostModel][X86] Declare costs variables based on type
The alphabetical progression isn't that useful

llvm-svn: 305808
2017-06-20 17:04:46 +00:00
Craig Topper
fac5b9df49 [TableGen] Take a parameter by reference instead of pointer so we don't have to add & on both callers. NFC
llvm-svn: 305807
2017-06-20 16:34:37 +00:00
Craig Topper
0391f937fe [TableGen] Use range based for loop. NFC
llvm-svn: 305806
2017-06-20 16:34:35 +00:00
Yuka Takahashi
3b19a660ec [GSoC] Flag value completion for clang
This is patch for GSoC project, bash-completion for clang.

To use this on bash, please run `source clang/utils/bash-autocomplete.sh`.
bash-autocomplete.sh is code for bash-completion.

In this patch, Options.td was mainly changed in order to add value class
in Options.inc.

llvm-svn: 305805
2017-06-20 16:31:31 +00:00
Sanjay Patel
f4fed2c4b8 [x86] enable CGP memcmp() expansion for 2/4/8 byte sizes
There are a couple of potential improvements as seen in the IR and asm:
1. We're unnecessarily extending to a larger type to compare values.
2. The codegen for (select cond, 1, -1) could avoid a cmov.
(or we could change the order of the compares, so we have a select with 0 operand)

llvm-svn: 305802
2017-06-20 15:58:30 +00:00
Simon Pilgrim
df21643743 [X86][SSE] Relax 0/-1 vector element insertion to work for any vector with >=16bit elements
Shuffle lowering/combining now does a good job for 256/512-bit vectors - we don't need to prevent this

llvm-svn: 305801
2017-06-20 15:19:02 +00:00
Tim Northover
a30b7057aa DAG: correctly legalize UMULO.
We were incorrectly sign extending into the high word (as you would for
SMULO) when legalizing UMULO in terms of a wider full multiplication.

Patch by James Duley.

llvm-svn: 305800
2017-06-20 15:01:38 +00:00
Vassil Vassilev
b1c3f2425a D33466: Make file non-executable.
llvm-svn: 305795
2017-06-20 14:20:48 +00:00
Sanjay Patel
2cd42e59fa [InstCombine] fix code/test comments for r305792; NFC
These diffs were in the last version of the patch in D33342,
but I accidentally committed the previous rev. 

llvm-svn: 305793
2017-06-20 12:45:46 +00:00
Sanjay Patel
b1e57ed5ec [InstCombine] try to canonicalize xor-of-icmps to and-of-icmps
We have a large portfolio of folds for and-of-icmps and or-of-icmps in InstSimplify and InstCombine, 
but hardly anything for xor-of-icmps. Rather than trying to rethink and translate all of those folds, 
we can use the truth table definition of xor:

X ^ Y --> (X | Y) & !(X & Y)

...to see if we can convert the xor to and/or and then use the existing folds.

http://rise4fun.com/Alive/J9v

Differential Revision: https://reviews.llvm.org/D33342

llvm-svn: 305792
2017-06-20 12:40:55 +00:00
Daniel Sanders
0c5795464b [globalisel][tablegen] Add support for COPY_TO_REGCLASS.
Summary:
As part of this
* Emitted instructions now have named MachineInstr variables associated
  with them. This isn't particularly important yet but it's a small step
  towards multiple-insn emission.
* constrainSelectedInstRegOperands() is no longer hardcoded. It's now added
  as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses
  an alternate constraint mechanism ConstrainOperandToRegClassAction() which
  supports arbitrary constraints such as that defined by COPY_TO_REGCLASS.

Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar

Reviewed By: ab

Subscribers: javed.absar, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D33590

llvm-svn: 305791
2017-06-20 12:36:34 +00:00
Simon Pilgrim
a081b25bbc Fix Wdocumentation warning
llvm-svn: 305790
2017-06-20 12:28:33 +00:00
Simon Pilgrim
8890df3f13 [X86][SSE] Dropped old INSERT_VECTOR_ELT lowering TODO
Target shuffle combining now supports the matching of INSERT_VECTOR_ELT/PINSRW/PINSRB for merging multiple insertions into shuffles/bitmasks.

llvm-svn: 305788
2017-06-20 10:33:34 +00:00
Simon Pilgrim
fb1bb45c57 Fixed test name. NFCI.
llvm-svn: 305787
2017-06-20 10:24:06 +00:00
Igor Breger
812ef348d0 [GlobalISel][X86] fix compilation error ( -Werror=unused-function )
llvm-svn: 305786
2017-06-20 09:40:57 +00:00
Haojian Wu
d2efe6d376 [SelectionDAG] Fix an use-after-free issue introduced in r305775.
vector.back() will be invalidated when memory reallocation happens.

llvm-svn: 305785
2017-06-20 09:29:43 +00:00
Igor Breger
4e3209ead1 [GlobalISel][X86] Get correct RegClass for given RegBank.
Summary:
In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665

Reviewers: qcolombet, t.p.northover, zvi, guyblank

Reviewed By: t.p.northover, guyblank

Subscribers: guyblank, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D33952

Conflicts:
	test/CodeGen/X86/GlobalISel/select-memop-scalar.mir

llvm-svn: 305784
2017-06-20 09:15:10 +00:00
Igor Breger
078eb813d6 [GlobalISel] combine not symmetric merge/unmerge nodes.
Summary:
In some cases legalization ends up with not symmetric merge/unmerge nodes.
Transform it to merge/unmerge nodes.

Reviewers: t.p.northover, qcolombet, zvi

Reviewed By: t.p.northover

Subscribers: rovka, kristof.beyls, guyblank, llvm-commits

Differential Revision: https://reviews.llvm.org/D33626

llvm-svn: 305783
2017-06-20 08:54:17 +00:00
Max Kazantsev
c0bcdacb00 [SCEV][NFC] Fix a misleading description of AddOpsInlineThreshold
The description of this option was copy-pasted from another one and does not
correspond to reality.

Differential Revision: https://reviews.llvm.org/D34390

llvm-svn: 305782
2017-06-20 08:37:31 +00:00
Igor Breger
3c1f43a412 [GlobalISel][X86] add legalizer mir tests. NFC
llvm-svn: 305781
2017-06-20 08:30:48 +00:00
NAKAMURA Takumi
f47dcd2ae3 WasmObjectWriter.cpp: Tweak a comment line. [-Wdocumentation]
llvm-svn: 305777
2017-06-20 07:21:19 +00:00
Alexandros Lamprineas
4796e0f03c [ARM] Support constant pools in data when generating execute-only code.
Resubmission of r305387, which was reverted at r305390. The Address
Sanitizer caught a stack-use-after-scope of a Twine variable. This
is now fixed by passing the Twine directly as a function parameter.

The ARM backend asserts against constant pool lowering when it generates
execute-only code in order to prevent the generation of constant pools in
the text section. It appears that target independent optimizations might
generate DAG nodes that represent constant pools. By lowering such nodes
as global addresses we don't violate the semantics of execute-only code
and also it is guaranteed that execute-only behaves correct with the
position-independent addressing modes that support execute-only code.

Differential Revision: https://reviews.llvm.org/D33773

llvm-svn: 305776
2017-06-20 07:20:52 +00:00
Max Kazantsev
178450709e [SelectionDAG] Get rid of recursion in CalcNodeSethiUllmanNumber
The recursive implementation of CalcNodeSethiUllmanNumber may
overflow stack on extremely long pred chains. This patch replaces it
with an equivalent iterative implementation.

Differential Revision: https://reviews.llvm.org/D33769

llvm-svn: 305775
2017-06-20 07:07:09 +00:00
Sam Clegg
22ea3d5964 Fix unused function build error in lld
The lld-x86_64-darwin13 is failing with:
 error: unused function 'operator<<'

Wrap the declation in ifndef NDEBUG, which matches
what is done in MipsELFObjectWriter.cpp.

Differential Revision: https://reviews.llvm.org/D34384

llvm-svn: 305771
2017-06-20 05:05:10 +00:00
Sam Clegg
3393d8be1b [WebAssembly] Fix build failures introduced in r305769
This fixes two build failures that only occur in certain
configurations:
- error: unused function 'operator<<'
- error: control reaches end of non-void function

Differential Revision: https://reviews.llvm.org/D34382

llvm-svn: 305770
2017-06-20 04:47:58 +00:00
Sam Clegg
add57cc355 [WebAssembly] Add support for weak symbols in the binary format
This also introduces the updated format for the
"linking" section which can represent extra
symbol information.  See:
https://github.com/WebAssembly/tool-conventions/pull/10

Differential Revision: https://reviews.llvm.org/D34019

llvm-svn: 305769
2017-06-20 04:04:59 +00:00
Nirav Dave
2d9d97ed85 [DAG] Simplify BaseIndexOffset. NFCI.
Remove tail calls and cleanup codeflow.

llvm-svn: 305768
2017-06-20 02:48:39 +00:00
Vedant Kumar
5dd7f329b9 [Coverage] PR33517: Check for failure to load func records
With PR33517, it became apparent that symbol table creation can fail
when presented with malformed inputs. This patch makes that sort of
error detectable, so llvm-cov etc. can fail more gracefully.

Specifically, we now check that function records loaded from corrupted coverage
mapping data are rejected, e.g when the recorded function name is garbage.

Testing: check-{llvm,clang,profile}, some unit test updates.
llvm-svn: 305767
2017-06-20 02:05:35 +00:00
Vedant Kumar
30059fc639 [ProfileData] PR33517: Check for failure of symtab creation
With PR33517, it became apparent that symbol table creation can fail
when presented with malformed inputs. This patch makes that sort of
error detectable, so llvm-cov etc. can fail more gracefully.

Specifically, we now check that function names within the symbol table
aren't empty.

Testing: check-{llvm,clang,profile}, some unit test updates.
llvm-svn: 305765
2017-06-20 01:38:56 +00:00
Pengxuan Zheng
4bf7cb91e6 [test-release.sh] Enable Polly by default
Reviewers: grosser, hans, zinob, bollu

Reviewed By: grosser, hans

Subscribers: tstellar, llvm-commits

Differential Revision: https://reviews.llvm.org/D34306

llvm-svn: 305763
2017-06-20 01:04:25 +00:00