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Commit Graph

89733 Commits

Author SHA1 Message Date
Bill Wendling
eecb534c87 Implement the NoBuiltin attribute.
The 'nobuiltin' attribute is applied to call sites to indicate that LLVM should
not treat the callee function as a built-in function. I.e., it shouldn't try to
replace that function with different code.

llvm-svn: 175835
2013-02-22 00:12:35 +00:00
Cameron Zwarich
ce9cf63b6f Stop relying on physical register kill flags in isKilled() in the two-address
pass. One of the callers of isKilled() can cope with overapproximation of kills
and the other can't, so I added a flag to indicate this.

In theory this could pessimize code slightly, but in practice most physical
register uses are kills, and most important kills of physical registers are the
only uses of that register prior to register allocation, so we can recognize
them as kills even without kill flags.

This is relevant because LiveIntervals gets rid of all kill flags.

llvm-svn: 175821
2013-02-21 22:58:42 +00:00
Eli Bendersky
1185958e53 Previously, parsing capability of the .debug_frame section was added
to lib/DebugInfo, with dumping in llvm-dwarfdump. This patch adds
initial ability to parse and dump CFA instructions contained in
entries.

To keep it manageable, the patch omits some more advanced capabilities
(accounted in TODOs):

* Parsing of instructions with BLOCK arguments (expression lists)
* Dumping of actual instruction arguments (currently only names are
dumped). This is quite tricky since the dumper has to effectively
"interpret" the instructions.

llvm-svn: 175820
2013-02-21 22:53:19 +00:00
David Blaikie
fb0bcc1539 Limit cast machinery to preserve const and not accept temporaries
After cleaning up the following type hierarchies:
  * TypeLoc: r175462
  * SVal: r175594
  * CFGElement: r175462
  * ProgramPoint: r175812
that all invoked undefined behavior by causing a derived copy construction of a
base object through an invalid cast (thus supporting code that relied on
casting temporaries that were direct base objects) Clang/LLVM is now clean of
casts of temporaries. So here's some fun SFINAE machinery (courtesy of Eli
Friedman, with some porting back from C++11 to LLVM's traits by me) to cause
compile-time failures if llvm::cast & friends are ever passed an rvalue.

This should avoid a repeat of anything even remotely like PR14321/r168124.

Thanks to Jordan Rose for the help with the various Static Analyzer related
hierarchies that needed cleaning up, Eli for the SFINAE, Richard Smith, John
McCall, Ted Kremenek, and Anna Zaks for their input/reviews/patience along the
way.

llvm-svn: 175819
2013-02-21 22:48:34 +00:00
Renato Golin
d371b2ca14 Allow GlobalValues to vectorize with AliasAnalysis
Storing the load/store instructions with the values
and inspect them using Alias Analysis to make sure
they don't alias, since the GEP pointer operand doesn't
take the offset into account.

Trying hard to not add any extra cost to loads and stores
that don't overlap on global values, AA is *only* calculated
if all of the previous attempts failed.

Using biggest vector register size as the stride for the
vectorization access, as we're being conservative and
the cost model (which calculates the real vectorization
factor) is only run after the legalization phase.

We might re-think this relationship in the future, but
for now, I'd rather be safe than sorry.

llvm-svn: 175818
2013-02-21 22:39:03 +00:00
Lang Hames
ab1db3b10b Re-apply r175688, with the changes suggested by Jakob in PR15320.
llvm-svn: 175809
2013-02-21 22:16:43 +00:00
Chad Rosier
d3dde59198 Remove dead code and whitespace.
llvm-svn: 175804
2013-02-21 21:40:51 +00:00
Pedro Artigas
c2a923e628 Clear the whole table including the tombstones, since the tombstone count will
be set to zero that is what it was intended. Should improve performance of 
the data structure when clear is invoked frequently (both compile time and
memory usage).

llvm-svn: 175799
2013-02-21 21:32:00 +00:00
Eli Bendersky
37f247b8d8 Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.

llvm-svn: 175788
2013-02-21 20:05:00 +00:00
Bill Wendling
34f1dacd7d Don't assert on empty attributes.
llvm-svn: 175785
2013-02-21 19:46:51 +00:00
Anshuman Dasgupta
810cccb843 Hexagon: Expand cttz, ctlz, and ctpop for now.
llvm-svn: 175783
2013-02-21 19:39:40 +00:00
Jakob Stoklund Olesen
38b12c2ce2 Make RAFast::UsedInInstr indexed by register units.
This fixes some problems with too conservative checking where we were
marking all aliases of a register as used, and then also checking all
aliases when allocating a register.

<rdar://problem/13249625>

llvm-svn: 175782
2013-02-21 19:35:21 +00:00
Evan Cheng
7ccccd2f99 Radar numbers don't belong in source code.
llvm-svn: 175775
2013-02-21 18:37:54 +00:00
Bill Schmidt
396d92f47f Trivial cleanup
llvm-svn: 175771
2013-02-21 17:26:05 +00:00
Paul Redmond
407a1f751a add missing space which prevented the llvm.loop code-block from appearing in the
generated html.

llvm-svn: 175769
2013-02-21 17:20:45 +00:00
Bill Schmidt
049ba390f5 Large code model support for PowerPC.
Large code model is identical to medium code model except that the
addis/addi sequence for "local" accesses is never used.  All accesses
use the addis/ld sequence.

The coding changes are straightforward; most of the patch is taken up
with creating variants of the medium model tests for large model.

llvm-svn: 175767
2013-02-21 17:12:27 +00:00
Lang Hames
8ae5071d98 Revert r175688 - It broke a test case (see PR15320).
llvm-svn: 175765
2013-02-21 17:01:59 +00:00
Eli Bendersky
79457c8f90 getX86SubSuperRegister has a special mode with High=true for i64 which
exists solely to enable it to call itself for i8 with some registers.
The proposed patch simplifies the function somewhat to make the High
bit only meaningful for the i8 mode, which makes sense. No functional
difference (getX86SubSuperRegister is not getting called from anywhere
outside with i64 and High=true).

llvm-svn: 175762
2013-02-21 16:40:18 +00:00
Benjamin Kramer
9de866701b DAGCombiner: Make the post-legalize vector op optimization more aggressive.
A legal BUILD_VECTOR goes in and gets constant folded into another legal
BUILD_VECTOR so we don't lose any legality here. The problematic PPC
optimization that made this check necessary was fixed recently.

llvm-svn: 175759
2013-02-21 15:24:35 +00:00
Christian Konig
8638b12ee3 R600/SI: inline V_ADD|SUB_F32 patterns
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175758
2013-02-21 15:17:41 +00:00
Christian Konig
824109b274 R600/SI: replace IMPLICIT_DEF with SIOperand.ZERO
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175757
2013-02-21 15:17:36 +00:00
Christian Konig
5658281922 R600/SI: replace SI_V_CNDLT with a pattern
It actually fixes quite a bunch of piglit tests.

This is a candidate for the mesa-stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175756
2013-02-21 15:17:32 +00:00
Christian Konig
e7cd353b34 R600/SI: use patterns for clamp, fabs, fneg
Instead of using custom inserters, it's simpler and
should make DAG folding easier.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175755
2013-02-21 15:17:27 +00:00
Christian Konig
046d32096b R600/SI: add all the other missing asm operands v2
v2: put implicit parameters in []

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175754
2013-02-21 15:17:22 +00:00
Christian Konig
bab22f59b9 R600/SI: add the missing M*BUF|IMG asm operands
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175753
2013-02-21 15:17:17 +00:00
Christian Konig
d9de20769d R600/SI: add the missing S_* asm operands
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175752
2013-02-21 15:17:13 +00:00
Christian Konig
a544d6c0b9 R600/SI: rework VOP3 classes
Order the classes and add asm operands.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175751
2013-02-21 15:17:09 +00:00
Christian Konig
049fe6c2a3 R600/SI: simplify VOPC_* pattern v2
Fixing asm operation names.

v2: fix name of the e64 encoding, also add asm operands

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175750
2013-02-21 15:17:04 +00:00
Christian Konig
77ce064675 R600/SI: rework VOP2_* pattern v2
Fixing asm operation names.

v2: use ZERO constant, also add asm operands

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175749
2013-02-21 15:16:58 +00:00
Christian Konig
5329724e84 R600/SI: rework VOP1_* patterns v2
Fixing asm operation names.

v2: use ZERO constant, also add asm operands

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175748
2013-02-21 15:16:53 +00:00
Christian Konig
3d59611438 R600/SI: add constant for inline zero operand
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175747
2013-02-21 15:16:49 +00:00
Christian Konig
b5291fd25d R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td
Those two files got mixed up.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 175746
2013-02-21 15:16:44 +00:00
Tom Stellard
aa63f0e8d4 R600: Fix for Unigine when MachineSched is enabled
Fixes for-loop.cl piglit test

Patch By: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175742
2013-02-21 15:06:59 +00:00
Bill Schmidt
4a815e468d Code review cleanup for r175697
llvm-svn: 175739
2013-02-21 14:35:42 +00:00
Michel Danzer
756af8b106 R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32
NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175733
2013-02-21 08:57:10 +00:00
Cameron Zwarich
a3404085e3 Don't rely on the isDead() MachineOperand flag when updating LiveIntervals.
llvm-svn: 175732
2013-02-21 08:51:58 +00:00
Cameron Zwarich
b5e706c80e Use getInterval() instead of getOrCreateInterval().
llvm-svn: 175731
2013-02-21 08:51:55 +00:00
David Blaikie
b39f6eaf73 Only include move-related Optional<T> tests when rvalue references are available.
llvm-svn: 175730
2013-02-21 07:58:45 +00:00
David Blaikie
117a44bd1a Add move ctor/assignment to Optional<T>
Code review feedback for r175580 by Jordan Rose.

llvm-svn: 175729
2013-02-21 07:55:39 +00:00
Cameron Zwarich
6a519a9c72 Make another kill check LiveIntervals-aware.
This brings the number of remaining failures in 'make check' without
LiveVariables down to 39, with 1 unexpectedly passing test.

llvm-svn: 175727
2013-02-21 07:02:30 +00:00
Cameron Zwarich
99c801fdb7 Split part of isKilled() into a separate function for use elsewhere.
llvm-svn: 175726
2013-02-21 07:02:28 +00:00
David Blaikie
2e8e3f41e9 Correct spelling of 'enumerator'.
Post commit code review feedback to r175705 from Jordan Rose.

llvm-svn: 175724
2013-02-21 06:08:22 +00:00
David Blaikie
6739305653 Make Optional<T>'s operator bool 'explicit' in C++11
Provides a general way to add 'explicit' for conversion operators (a no-op when
compiling as C++98).

llvm-svn: 175723
2013-02-21 06:05:57 +00:00
Cameron Zwarich
59bb2dbaf6 Update isKilledAt in TwoAddressInstructionPass.cpp to use LiveIntervals when
available.

With this commit there are no longer any assertion or verifier failures when
running 'make check' without LiveVariables. There are still 56 failing tests
with codegen differences and 1 unexpectedly passing test.

llvm-svn: 175719
2013-02-21 04:33:02 +00:00
Reed Kotler
276bb6b70b Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.

llvm-svn: 175718
2013-02-21 04:22:38 +00:00
NAKAMURA Takumi
398640076e ADT/Optional.h: Appease msvc. It reapplies r175626.
llvm-svn: 175710
2013-02-21 02:32:25 +00:00
Michael J. Spencer
25f5a420ec [objdump] Add PT_PHDR.
llvm-svn: 175709
2013-02-21 02:21:29 +00:00
Jack Carter
0f776a392d Mips specific standalone assembler addressing mode %hi and %lo.
The constructs %hi() and %lo() represent the high and low 16 
bits of the address. 
Because the 16 bit offset field of an LW instruction is 
interpreted as signed, if bit 15 of the low part is 1 then the 
low part will act as a negative and 1 needs to be added to the 
high part.

Contributer: Vladimir Medic
llvm-svn: 175707
2013-02-21 02:09:31 +00:00
Bill Schmidt
0e7935e723 PPCDAGToDAGISel::PostprocessISelDAG()
This patch implements the PPCDAGToDAGISel::PostprocessISelDAG virtual
method to perform post-selection peephole optimizations on the DAG
representation.

One optimization is implemented here:  folds to clean up complex
addressing expressions for thread-local storage and medium code
model.  It will also be useful for large code model sequences when
those are added later.  I originally thought about doing this on the
MI representation prior to register assignment, but it's difficult to
do effective global dead code elimination at that point.  DCE is
trivial on the DAG representation.

A typical example of a candidate code sequence in assembly:

   addis 3, 2, globalvar@toc@ha
   addi  3, 3, globalvar@toc@l
   lwz   5, 0(3)

When the final instruction is a load or store with an immediate offset
of zero, the offset from the add-immediate can replace the zero,
provided the relocation information is carried along:

   addis 3, 2, globalvar@toc@ha
   lwz   5, globalvar@toc@l(3)

Since the addi can in general have multiple uses, we need to only
delete the instruction when the last use is removed.

llvm-svn: 175697
2013-02-21 00:38:25 +00:00
David Blaikie
7c7579badf Provide a "None" value for convenience when using Optional<T>()
This implementation of NoneType/None does have some holes but I haven't
found one that doesn't - open to improvement.

llvm-svn: 175696
2013-02-21 00:27:28 +00:00