1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
Commit Graph

201388 Commits

Author SHA1 Message Date
Denis Antrushin
f0a68d4ee0 [Statepoints] Operand folding in presense of tied registers.
Implement proper folding of statepoint meta operands (deopt and GC)
when statepoint uses tied registers.
For deopt operands it is just about properly preserving tiedness
in new instruction.
For tied GC operands folding is a little bit more tricky.
We can fold tied GC operands only from InlineSpiller, because it knows
how to properly reload tied def after it was turned into memory operand.
Other users (e.g. peephole) cannot properly fold such operands as they
do not know how (or when) to reload them from memory.
We do this by un-tieing operand we want to fold in InlineSpiller
and allowing to fold only untied operands in foldPatchpoint.
2020-08-05 20:18:28 +07:00
Roman Lebedev
c3ca06f18c Recommit "[InstCombine] Negator: -(X << C) --> X * (-1 << C)"
This reverts commit ac70b37a00dc02bd8923e0a4602d26be4581c570
which reverted commit 8aeb2fe13a4100b4c2e78d6ef75119304100cb1f
because codegen tests got broken and i needed time to investigate.

This shows some regressions in tests, but they are all around GEP's,
so i'm not really sure how important those are.

https://rise4fun.com/Alive/1Gn
2020-08-05 15:59:13 +03:00
Nico Weber
30c0f960b8 [gn build] (manually) merge 3ab01550b
This reverts commit 0bbaacc8cae0373d4500c4e3f6f128d21f9033b7 and
2ad56119f5dc6c6af2b8ddfd9fc8c6460a7507c8 which merged 10b1b4a23
(and follow-ups), since that change was reverted in 3ab01550b.
2020-08-05 08:56:14 -04:00
Sam Parker
986b770698 [ARM][CostModel] Implement getCFInstrCost
As with other targets, set the throughput cost of control-flow
instructions to free so that we don't miss out of vectorization
opportunities.

Differential Revision: https://reviews.llvm.org/D85283
2020-08-05 12:44:51 +01:00
Simon Pilgrim
7502dabc07 DWARFVerifier.h - remove unnecessary forward declarations and includes. NFCI. 2020-08-05 12:42:44 +01:00
Xing GUO
7e07ca06a4 [obj2yaml] Add support for dumping the .debug_aranges section.
This patch adds support for dumping DWARF sections to obj2yaml. The
.debug_aranges section is used to illustrate the basic idea.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D85094
2020-08-05 19:19:05 +08:00
Simon Pilgrim
e9e363a4b8 GISelWorkList.h - remove unnecessary includes. NFCI. 2020-08-05 12:00:28 +01:00
Simon Pilgrim
8d6d113d6f CallLowering.h - remove unnecessary CCState forward declaration. NFCI.
Already defined in CallingConvLower.h
2020-08-05 12:00:28 +01:00
Simon Pilgrim
c50326eaac [X86][AVX] Add test showing unnecessary duplicate HADD instructions
Taken from internal fuzz test
2020-08-05 12:00:27 +01:00
Hans Wennborg
c132b24d91 Revert "[CMake] Simplify CMake handling for zlib"
This quietly disabled use of zlib on Windows even when building with
-DLLVM_ENABLE_ZLIB=FORCE_ON.

> Rather than handling zlib handling manually, use find_package from CMake
> to find zlib properly. Use this to normalize the LLVM_ENABLE_ZLIB,
> HAVE_ZLIB, HAVE_ZLIB_H. Furthermore, require zlib if LLVM_ENABLE_ZLIB is
> set to YES, which requires the distributor to explicitly select whether
> zlib is enabled or not. This simplifies the CMake handling and usage in
> the rest of the tooling.
>
> This is a reland of abb0075 with all followup changes and fixes that
> should address issues that were reported in PR44780.
>
> Differential Revision: https://reviews.llvm.org/D79219

This reverts commit 10b1b4a231a485f1711d576e6131f6755e008abe and follow-ups
64d99cc6abed78c00a2a7863b02ce54911a5264f and
f9fec0447e12da9e8cf4b628f6d45f4941e7d182.
2020-08-05 12:31:44 +02:00
Paul Walker
3c5c30be96 [SVE] Add lowering for fixed length vector and, or & xor operations.
Since there are no ill effects when performing these operations
with undefined elements, they are lowered to the already supported
unpredicated scalable vector equivalents.

Differential Revision: https://reviews.llvm.org/D85117
2020-08-05 11:28:34 +01:00
Simon Pilgrim
850778022a [DAG] Fold vector (aext (load x)) -> (zext (truncate (zextload x)))
We currently don't do anything to fold any_extend vector loads as no target has such an instruction.

Instead I've added support for folding to a zextload, SimplifyDemandedBits does a good job of adjusting the zext(truncate(()) stages as required later on.

We still need the custom scalar extload handling instead of using the tryToFoldExtOfLoad helper as it has different legality tests - we can probably tweak that to reduce most of the code duplication.

Fixes the regression I mentioned in rG99a971cadff7

Differential Revision: https://reviews.llvm.org/D85129
2020-08-05 11:22:23 +01:00
Georgii Rymar
af54a4ae5b [llvm-readobj/elf] - Add a testing for --stackmap and refine the implementation.
Currently, we only test the `--stackmap` option here:
https://github.com/llvm/llvm-project/blob/master/llvm/test/Object/stackmap-dump.test
it uses a precompiled MachO binary currently and I've found no tests for this option for ELF.

The implementation also has issues. For example, it might assert on a wrong version
of the .llvm-stackmaps section. Or it might crash on an empty or truncated section.

This patch introduces a new tools/llvm-readobj/ELF test file as well as implements a few
basic checks to catch simple crashes/issues

It also eliminates `unwrapOrError` calls in `printStackMap()`.

Differential revision: https://reviews.llvm.org/D85208
2020-08-05 13:09:04 +03:00
Benjamin Kramer
eacb852738 [llvm-symbolizer] Add legacy aliases -demangle=true and -demangle=false.
This is used in the wild, don't break compatibility for no good reason.
https://github.com/google/pprof/blob/master/internal/binutils/addr2liner_llvm.go
2020-08-05 12:07:46 +02:00
Jordan Rupprecht
8003b49524 [docs] Document pattern of using CHECK-SAME to skip irrelevant lines
This came up during the review for D67656. It's nice but also subtle, so documenting it as an idiom will make tests easier to understand.

Reviewed By: probinson

Differential Revision: https://reviews.llvm.org/D68061
2020-08-05 11:03:56 +01:00
David Turner
221f10ac36 Do not map read-only data memory sections with EXECUTE flags.
The code in SectionMemoryManager.cpp unnecessarily maps
read-only data sections with the READ+EXECUTE flags. This is
undesirable from a security stand-point.

Moreover, on the Fuchsia platform, which is now very strict
about mapping pages with the EXECUTE permission, this simply
fails, because the section's pages were initially allocated
with only the READ+WRITE flags.

A more detailed description of the issue can be found in this
public SwiftShader bug:

  https://issuetracker.google.com/issues/154586551

This patch just restrict the mapping to the READ flag for ROData
sections. Code sections are still mapped with READ+EXECUTE as
expected.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D78574
2020-08-05 10:51:48 +02:00
Sander de Smalen
8489fbb9a7 [AArch64][SVE] Disable tail calls if callee does not preserve SVE regs.
This fixes an issue triggered by the following code, where emitEpilogue
got confused when trying to restore the SVE registers after the call,
whereas the call to bar() is implemented as a TCReturn:

  int non_sve();
  int sve(svint32_t x) { return non_sve(); }

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D84869
2020-08-05 09:38:54 +01:00
Jay Foad
b212a3e9c6 [AMDGPU] Propagate fast math flags in frem lowering
Differential Revision: https://reviews.llvm.org/D84518
2020-08-05 09:09:38 +01:00
Jay Foad
7ed52065b8 [AMDGPU] Precommit tests for D84518 Propagate fast math flags in frem lowering 2020-08-05 09:09:02 +01:00
Jay Foad
f5c2a38331 [AMDGPU] Lower frem f16
Without this it would fail to select on subtargets that have 16-bit
instructions.

Differential Revision: https://reviews.llvm.org/D84517
2020-08-05 09:08:40 +01:00
Yevgeny Rouban
e8fe9281f9 DomTree: Make PostDomTree indifferent to block successors swap
Fixed the commit c35585e209efe69e2233bdc5ecd23bed7b735ba3.

This is a fix for the bug 46098 where PostDominatorTree
is unexpectedly changed by InstCombine's branch swapping
transformation.
This patch fixes PostDomTree builder. While looking for
the furthest away node in a reverse unreachable subgraph
this patch runs DFS with successors in their function order.
This order is indifferent to the order of successors, so is
the furthest away node.

Reviewers: kuhar, nikic, lebedev.ri
Differential Revision: https://reviews.llvm.org/D84763
2020-08-05 14:26:32 +07:00
Martin Storsjö
b52b24c898 [llvm-rc] Allow string table values split into multiple string literals
This can practically easily be a product of combining strings with
macros in resource files.

This fixes https://github.com/mstorsjo/llvm-mingw/issues/140.

As string literals within llvm-rc are handled as StringRefs, each
referencing an uninterpreted slice of the input file, with actual
interpretation of the input string (codepage handling, unescaping etc)
done only right before writing them out to disk, it's hard to
concatenate them other than just bundling them up in a vector,
without rearchitecting a large part of llvm-rc.

This matches how the same already is supported in VersionInfoValue,
with a std::vector<IntOrString> Values.

MS rc.exe only supports concatenated string literals in version info
values (already supported), string tables (implemented in this patch)
and user data resources (easily implemented in a separate patch, but
hasn't been requested by any end user yet), while GNU windres supports
string immediates split into multiple strings anywhere (e.g. like
(100 ICON "myicon" ".ico"). Not sure if concatenation in other
statements actually is used in the wild though, in resource files
normally built by GNU windres.

Differential Revision: https://reviews.llvm.org/D85183
2020-08-05 08:59:32 +03:00
Juneyoung Lee
e8ae34c075 [JumpThreading] Consider freeze as a zero-cost instruction
This is a simple patch that makes freeze as a zero-cost instruction, as bitcast already is.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D85023
2020-08-05 14:42:36 +09:00
Juneyoung Lee
7bdb67cea7 [JumpThreading] Add a test for D85023; NFC 2020-08-05 13:40:14 +09:00
Mehdi Amini
c8fb2f08a3 Revert "DomTree: Make PostDomTree immune to block successors swap"
This reverts commit c35585e209efe69e2233bdc5ecd23bed7b735ba3.

The MLIR is broken with this patch, reproduce by adding
-DLLVM_ENABLE_PROJECTS=mlir to the cmake configuration and
build `ninja tools/mlir/lib/IR/CMakeFiles/obj.MLIRIR.dir/Dominance.cpp.o`
2020-08-05 04:32:44 +00:00
Evgeniy Brevnov
08e662f69a [BPI][NFC] Unify handling of normal and SCC based loops
This is one more NFC part extracted from D79485. Normal and SCC based loops have very different representation and have to be handled separatly each time we deal with loops. D79485 is going to introduce much more extensive use of loops what will be problematic with out this change.

Reviewed By: davidxl

Differential Revision: https://reviews.llvm.org/D84838
2020-08-05 11:19:24 +07:00
Yevgeny Rouban
dd982a9b72 DomTree: Make PostDomTree immune to block successors swap
This is another fix for the bug 46098 where PostDominatorTree
is unexpectedly changed by InstCombine's branch swapping
transformation.
This patch fixes PostDomTree builder. While looking for
the furthest away node in a reverse unreachable subgraph
this patch runs DFS with successors in their function order.
This order is indifferent to the order of successors, so is
the furthest away node.

Reviewers: kuhar, nikic, lebedev.ri
Differential Revision: https://reviews.llvm.org/D84763
2020-08-05 11:06:54 +07:00
Matt Arsenault
53bc9040d0 GlobalISel: Use buildAnyExtOrTrunc 2020-08-04 22:04:04 -04:00
Matt Arsenault
90be7019b8 GlobalISel: Simplify code
This cannot be a vector of pointers, so using getScalarSizeInBits just
added a bit extra noise.
2020-08-04 22:03:59 -04:00
Matt Arsenault
2fa463a27c GlobalISel: Fix redundant variable and shadowing 2020-08-04 22:03:55 -04:00
Matt Arsenault
dd7ad288a4 GlobalISel: Move load/store lowering to separate functions 2020-08-04 22:03:51 -04:00
Zequan Wu
425e233cb4 [llvm-cov] reset executation count to 0 after wrapped segment
Fix the bug: https://bugs.llvm.org/show_bug.cgi?id=36979. It also fixes this bug: https://bugs.llvm.org/show_bug.cgi?id=35404, which I think is caused by the same problem.

Differential Revision: https://reviews.llvm.org/D85036
2020-08-04 18:38:44 -07:00
Vitaly Buka
a4ce31d13f [StackSafety,NFC] Add combined index test
Missing file for the previous patch
2020-08-04 18:31:58 -07:00
Fangrui Song
ad19075904 [X86] Optimize getImpliedDisabledFeatures & getImpliedEnabledFeatures after D83273
Previously the time complexity is O(|number of paths from the root to an
implied feature| * CPU_FWATURE_MAX) where CPU_FEATURE_MAX is 92.

The number of paths can be large (theoretically exponential).

For an inline asm statement, there is a code path
`clang::Parser::ParseAsmStatement -> clang::Sema::ActOnGCCAsmStmt -> ASTContext::getFunctionFeatureMap`
leading to potentially many calls of getImpliedEnabledFeatures (41 for my -march=native case).

We should improve the performance a bit in case the number of inline asm
statements is large (Linux kernel builds).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D85257
2020-08-04 17:50:06 -07:00
Vitaly Buka
58827da30e [StackSafety,NFC] Add combined index test 2020-08-04 17:40:40 -07:00
Mircea Trofin
96e978c534 [llvm] Expose type and element count-related APIs on TensorSpec
Added a mechanism to check the element type, get the total element
count, and the size of an element.

Differential Revision: https://reviews.llvm.org/D85250
2020-08-04 17:32:16 -07:00
Roman Lebedev
44c1e6d7e7 Revert "[InstCombine] Negator: -(X << C) --> X * (-1 << C)"
Breaks codegen tests, will recommit later.

This reverts commit 8aeb2fe13a4100b4c2e78d6ef75119304100cb1f.
2020-08-05 03:19:38 +03:00
Roman Lebedev
364e286c57 [InstCombine] Negator: -(X << C) --> X * (-1 << C)
This shows some regressions in tests, but they are all around GEP's,
so i'm not really sure how important those are.

https://rise4fun.com/Alive/1Gn
2020-08-05 03:13:14 +03:00
Roman Lebedev
dbb4f844a8 [NFC][InstCombine] Fix value names (s/%tmp/%i/) and autogenerate a few tests being affected by negator change 2020-08-05 03:12:14 +03:00
Roman Lebedev
a3330725d7 [NFC][InstCombine] Negator: add tests for negation of left-shift by constant 2020-08-05 03:12:14 +03:00
Krzysztof Parzyszek
0ead9ed228 [RDF] Add operator<<(raw_ostream&, RegisterAggr), NFC 2020-08-04 18:40:07 -05:00
Krzysztof Parzyszek
242b3118d9 [RDF] Use hash-based containers, cache extra information
This improves performance.
2020-08-04 18:36:49 -05:00
Yonghong Song
2c21d9e520 BPF: simplify IR generation for __builtin_btf_type_id()
This patch simplified IR generation for __builtin_btf_type_id().
For __builtin_btf_type_id(obj, flag), previously IR builtin
looks like
   if (obj is a lvalue)
     llvm.bpf.btf.type.id(obj.ptr, 1, flag)  !type
   else
     llvm.bpf.btf.type.id(obj, 0, flag)  !type
The purpose of the 2nd argument is to differentiate
   __builtin_btf_type_id(obj, flag) where obj is a lvalue
vs.
   __builtin_btf_type_id(obj.ptr, flag)

Note that obj or obj.ptr is never used by the backend
and the `obj` argument is only used to derive the type.
This code sequence is subject to potential llvm CSE when
  - obj is the same .e.g., nullptr
  - flag is the same
  - metadata type is different, e.g., typedef of struct "s"
    and strust "s".
In the above, we don't want CSE since their metadata is different.

This patch change IR builtin to
   llvm.bpf.btf.type.id(seq_num, flag)  !type
and seq_num is always increasing. This will prevent potential
llvm CSE.

Also report an error if the type name is empty for
remote relocation since remote relocation needs non-empty
type name to do relocation against vmlinux.

Differential Revision: https://reviews.llvm.org/D85174
2020-08-04 16:29:42 -07:00
Krzysztof Parzyszek
66ffc7ab04 [RDF] Really remove remaining uses of PhysicalRegisterInfo::normalize 2020-08-04 18:23:38 -05:00
Krzysztof Parzyszek
a88523630e [RDF] Cache register aliases in PhysicalRegisterInfo
This improves performance of PhysicalRegisterInfo::makeRegRef.
2020-08-04 18:10:00 -05:00
Krzysztof Parzyszek
6f283737e5 [RDF] Lower the sorting complexity in RDFLiveness::getAllReachingDefs
The sorting is needed, because reaching defs are (logically) ordered,
but are not collected in that order. This change will break up the
single call to std::sort into a series of smaller sorts, each of which
should use a cheaper comparison function than the original.
2020-08-04 18:06:37 -05:00
Adrian Prantl
f44542f6a0 Teach SROA to handle allocas with more than one dbg.declare.
It is technically legal for optimizations to create an alloca that is
used by more than one dbg.declare, if one or both of them are inlined
instances of aliasing variables.

Differential Revision: https://reviews.llvm.org/D85172
2020-08-04 15:54:51 -07:00
Arthur Eubanks
ff7fade869 [Hexagon] Use InstSimplify instead of ConstantProp
This is the last remaining use of ConstantProp, migrate it to InstSimplify in the goal of removing ConstantProp.

Add -hexagon-instsimplify option to enable skipping of instsimplify in
tests that can't handle the extra optimization.

Differential Revision: https://reviews.llvm.org/D85047
2020-08-04 15:42:39 -07:00
Eli Friedman
83274f02e1 [SelectionDAG][SVE] Support scalable vectors in getConstantFP()
Differential Revision: https://reviews.llvm.org/D85249
2020-08-04 15:32:43 -07:00
Krzysztof Parzyszek
3bf7627b97 [RDF] Remove uses of RDFRegisters::normalize (deprecate)
This function has been reduced to an identity function for some time.
2020-08-04 17:02:12 -05:00