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164 Commits

Author SHA1 Message Date
Christopher Lamb
a26b82ea94 Fix a typo 
llvm-svn: 43144
 2007-10-18 19:28:55 +00:00
Evan Cheng
2e2d6358bc Change unfoldMemoryOperand(). User is now responsible for passing in the 
register used by the unfolded instructions. User can also specify whether to
unfold the load, the store, or both.

llvm-svn: 42946
 2007-10-13 02:35:06 +00:00
Evan Cheng
6e5205d379 Added storeRegToAddr, loadRegFromAddr, and unfoldMemoryOperand's. 
llvm-svn: 42624
 2007-10-05 01:34:55 +00:00
Evan Cheng
3537dbbd1e Refactor code to add load / store folded instructions -> register only 
instructions reverse map.

llvm-svn: 42509
 2007-10-01 23:44:33 +00:00
Evan Cheng
0f9e307353 - Added MRegisterInfo::getCrossCopyRegClass() hook. For register classes where reg to reg copies are not possible, this returns another register class which registers in the specified register class can be copied to (and copy back from). 
- X86 copyRegToReg() now supports copying between EFLAGS and GR32 / GR64 registers.

llvm-svn: 42372
 2007-09-26 21:31:07 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!

llvm-svn: 42346
 2007-09-26 06:25:56 +00:00
Evan Cheng
cb317912b2 Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses. 
llvm-svn: 41599
 2007-08-30 05:54:07 +00:00
Duncan Sands
26ef2a1767 Move getX86RegNum into X86RegisterInfo and use it 
in the trampoline lowering.  Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.

llvm-svn: 41577
 2007-08-29 19:01:20 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng
30e121adf6 Only adjust esp around calls in presence of alloca. 
llvm-svn: 40028
 2007-07-19 00:42:05 +00:00
Evan Cheng
532b73311e Use push / pop for prologues and epilogues. 
llvm-svn: 39967
 2007-07-17 07:59:08 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Evan Cheng
e47ec4d104 eliminateFrameIndex() change. 
llvm-svn: 36626
 2007-05-01 09:13:03 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Evan Cheng
116f97f2c7 PEI now passes a RegScavenger ptr to eliminateFrameIndex. 
llvm-svn: 34707
 2007-02-28 00:21:17 +00:00
Jim Laskey
6a937ad320 Support to provide exception and selector registers. 
llvm-svn: 34482
 2007-02-21 22:54:50 +00:00
Evan Cheng
e4ab9c032b Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. 
llvm-svn: 34428
 2007-02-19 21:49:54 +00:00
Reid Spencer
b27fcf3482 For PR1207: 
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.

llvm-svn: 34399
 2007-02-19 03:20:00 +00:00
Evan Cheng
8c2508f1ac Added getReservedRegs(). 
llvm-svn: 34376
 2007-02-17 11:06:00 +00:00
Jim Laskey
ba1dc7a8c7 Call frames for intel. 
llvm-svn: 33490
 2007-01-24 19:15:24 +00:00
Evan Cheng
d9d93832b0 hasFP() is now a virtual method of MRegisterInfo. 
llvm-svn: 33455
 2007-01-23 00:57:47 +00:00
Evan Cheng
bd6a333b52 Fix naming inconsistency. 
llvm-svn: 32823
 2007-01-02 21:33:40 +00:00
Jeff Cohen
e1003da1a2 Unbreak VC++ build. 
llvm-svn: 31464
 2006-11-05 19:31:28 +00:00
Evan Cheng
15dd42884e Committing X86-64 support. 
llvm-svn: 30177
 2006-09-08 06:48:29 +00:00
Chris Lattner
59a4d8dfcd Fix a long-standing wart in the code generator: two-address instruction lowering 
actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.

llvm-svn: 30108
 2006-09-05 02:12:02 +00:00
Evan Cheng
667b133ab9 getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 
llvm-svn: 28378
 2006-05-18 00:12:58 +00:00
Evan Cheng
84612a59c2 Better implementation of truncate. ISel matches it to a pseudo instruction 
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.

llvm-svn: 28119
 2006-05-05 05:40:20 +00:00
Jim Laskey
b93bc75add Foundation for call frame information. 
llvm-svn: 27491
 2006-04-07 16:34:46 +00:00
Jim Laskey
eb38a3e83a Expose base register for DwarfWriter. Refactor code accordingly. 
llvm-svn: 27225
 2006-03-28 13:48:33 +00:00
Jim Laskey
cec9c18c62 Add support to locate local variables in frames (early version.) 
llvm-svn: 26994
 2006-03-23 18:12:57 +00:00
Chris Lattner
15cb732cd7 Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) 
llvm-svn: 25913
 2006-02-02 20:12:32 +00:00
Chris Lattner
876bbd4faa add a method 
llvm-svn: 25910
 2006-02-02 19:57:16 +00:00
Chris Lattner
a1266f8ed5 Pass extra regclasses into spilling code 
llvm-svn: 23537
 2005-09-30 01:29:42 +00:00
Chris Lattner
4a8f6d97ff Implement the isLoadFromStackSlot interface 
llvm-svn: 23387
 2005-09-19 05:23:44 +00:00
Chris Lattner
e894de1791 The simple isel being gone makes this dead! 
llvm-svn: 22914
 2005-08-19 18:32:03 +00:00
Misha Brukman
bf3f6181fd * Remove trailing whitespace 
* Convert tabs to spaces

llvm-svn: 21426
 2005-04-21 23:38:14 +00:00
Chris Lattner
555a585fd8 Code insertion methods now return void instead of an int. 
llvm-svn: 15780
 2004-08-15 22:15:11 +00:00
Chris Lattner
e58190f5f6 These methods no longer take a TargetRegisterClass* operand. 
llvm-svn: 15774
 2004-08-15 21:56:44 +00:00
Nate Begeman
fabece673b Eliminate MachineFunction& argument from eliminateFrameIndex in x86 Target. Get MachineFunction from MachineInstruction's parent's parent 
llvm-svn: 15739
 2004-08-14 22:05:10 +00:00
Alkis Evlogimenos
2b94b048a9 Another API change to MRegisterInfo::foldMemoryOperand. Instead of a 
MachineBasicBlock::iterator take a MachineInstr*.

llvm-svn: 12392
 2004-03-14 20:14:27 +00:00
Alkis Evlogimenos
ff9482b664 Change MRegisterInfo::foldMemoryOperand to return the folded 
instruction to make the API more flexible.

llvm-svn: 12386
 2004-03-14 07:19:51 +00:00
Chris Lattner
e227ae6b88 Change to match the newer, simpler, interface 
llvm-svn: 11525
 2004-02-17 05:54:57 +00:00
Alkis Evlogimenos
c4ec9111bb Add API to check and fold memory operands into instructions. 
llvm-svn: 11519
 2004-02-17 04:33:18 +00:00
Chris Lattner
f28479d600 The prologue/epilogue related method calls have no reason to return a value, 
make them return void.

This allows us to avoid some costly MBB.size() calls

llvm-svn: 11448
 2004-02-14 19:49:54 +00:00
Alkis Evlogimenos
94cab18bdc Change interface so that we can add to the end of a basic block 
without getting an assertion from ilist that we are dereferencing
ilist<T>::end().

llvm-svn: 11345
 2004-02-12 08:11:04 +00:00
Alkis Evlogimenos
b755d35fd2 Change MachineBasicBlock's vector of MachineInstr pointers into an 
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.

llvm-svn: 11340
 2004-02-12 02:27:10 +00:00
Brian Gaeke
d25f86d683 Put all LLVM code into the llvm namespace, as per bug 109. 
llvm-svn: 9903
 2003-11-11 22:41:34 +00:00
Alkis Evlogimenos
c6a7c83333 Change all machine basic block modifier functions in MRegisterInfo to 
return the number of instructions added to/removed from the basic block
passed as their first argument.

Note: This is only needed because we use a std::vector instead of an
ilist to keep MachineBasicBlock instructions. Inserting an instruction
to a MachineBasicBlock invalidates all iterators to the basic
block. The return value can be used to update an index to the machine
basic block instruction vector and circumvent the iterator elimination
problem but this is really not needed if we move to a better
representation.

llvm-svn: 9704
 2003-11-04 22:57:09 +00:00
John Criswell
de34542f41 Added LLVM copyright header. 
llvm-svn: 9321
 2003-10-21 15:17:13 +00:00
Chris Lattner
457b33f7e4 Switch over to TableGen generated register file description 
llvm-svn: 7511
 2003-08-03 15:48:14 +00:00
Chris Lattner
8dce81478f This method is long dead 
llvm-svn: 7460
 2003-08-01 03:48:42 +00:00
Chris Lattner
56a499f4ee Changes to match new MRegisterInfo api 
llvm-svn: 5187
 2002-12-28 20:32:54 +00:00
Chris Lattner
34940d2aa8 Adjustments to match new simpler spill interface 
llvm-svn: 5147
 2002-12-25 05:06:43 +00:00
Chris Lattner
0b617b0e1d Update to use new interface for register info 
llvm-svn: 5098
 2002-12-17 04:19:17 +00:00
Chris Lattner
4214ac384a Simplify interfaces used by regalloc to insert code 
llvm-svn: 5052
 2002-12-15 20:06:35 +00:00
Chris Lattner
caa325a559 * Simplify TargetRegisterClass implementations 
* Change regclass iterators to use an extra level of pointers

llvm-svn: 5047
 2002-12-15 18:40:36 +00:00
Misha Brukman
fb02408496 Added moveReg2Reg() and moveImm2Reg() to accomodate moving data around due to 
PHI nodes.

llvm-svn: 5001
 2002-12-13 09:54:12 +00:00
Misha Brukman
7dc6877ce2 Implemented functions for emitting prologues and epilogues; 
removed EBP from the list of callee-saved registers (it isn't one).

llvm-svn: 4929
 2002-12-04 23:57:03 +00:00
Misha Brukman
101076f586 storeReg2RegOffset() and loadRegOffset2Reg() now take the iterator by value 
instead of by reference, since they return the modified iterator.

llvm-svn: 4914
 2002-12-04 17:14:13 +00:00
Misha Brukman
6e1c4851ea Moved buildReg2RegClassMap() into from X86RegisterInfo to MRegisterInfo, since 
it is target-independent.

llvm-svn: 4911
 2002-12-04 16:47:04 +00:00
Misha Brukman
5639a6279e Added support for callee- and caller-save registers. 
llvm-svn: 4897
 2002-12-03 23:11:21 +00:00
Misha Brukman
02c0acabb9 Added methods to read/write values to stack in .h, fixed implementation in 
.cpp to return the iterator correctly.

llvm-svn: 4827
 2002-11-22 22:43:47 +00:00
Misha Brukman
96283090dc Add definitions for function headers from MRegisterInfo.h: 
Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.

llvm-svn: 4784
 2002-11-20 18:59:43 +00:00
Chris Lattner
d25a097994 Initial checkin of X86 backend. 
We can instruction select exactly one instruction 'ret void'.  Wow.

llvm-svn: 4284
 2002-10-25 22:55:53 +00:00