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Author SHA1 Message Date
Bill Wendling
f3325864ce Build and install the archive when building the Apple way. 
llvm-svn: 135538
 2011-07-19 23:33:42 +00:00
Akira Hatanaka
a50bbdfe15 Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Evan Cheng
9a80b0a7e6 Fix an obvious typo that's preventing x86 (32-bit) from using .literal16. 
llvm-svn: 135535
 2011-07-19 23:14:32 +00:00
Eli Friedman
f809f44cf5 PR10386: Don't try to split an edge from an indirectbr. 
llvm-svn: 135534
 2011-07-19 22:59:41 +00:00
Benjamin Kramer
f5ca440fd0 Fix off-by-one. 
llvm-svn: 135533
 2011-07-19 22:59:25 +00:00
Jim Grosbach
e70c8eb49a Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
 2011-07-19 22:45:10 +00:00
Devang Patel
65afdd27d0 Distinguish between two copies of one inlined variable. 
llvm-svn: 135528
 2011-07-19 22:31:15 +00:00
Jim Grosbach
720b8c6578 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
 2011-07-19 21:59:29 +00:00
Owen Anderson
ad0f17c102 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM. 
llvm-svn: 135524
 2011-07-19 21:06:00 +00:00
Akira Hatanaka
cccc5fca34 Change variable name. 
llvm-svn: 135522
 2011-07-19 20:56:53 +00:00
Jim Grosbach
66af8b4a40 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. 
Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521
 2011-07-19 20:35:35 +00:00
Akira Hatanaka
14e517df43 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
 2011-07-19 20:34:00 +00:00
Jim Grosbach
40cce44255 Move mr[r]c[2] ARM tests and tidy up a bit. 
llvm-svn: 135517
 2011-07-19 20:28:56 +00:00
Jim Grosbach
69686aec2b ARM testcases for MOVT. 
llvm-svn: 135516
 2011-07-19 20:23:25 +00:00
Akira Hatanaka
b4db39fa83 Use descriptive variable names. 
llvm-svn: 135514
 2011-07-19 20:11:17 +00:00
Jim Grosbach
9debba28ed ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513
 2011-07-19 20:10:31 +00:00
Jim Grosbach
7e61a1ecf2 Tidy up. 
llvm-svn: 135507
 2011-07-19 19:47:11 +00:00
Jim Grosbach
8ebe7d700a Tighten conditional for 'mov' cc_out. 
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.

llvm-svn: 135506
 2011-07-19 19:45:44 +00:00
Devang Patel
5a4bb57ec5 Reapply r135457. This needs llvm-gcc change, that I forgot to check-in yesterday. 
llvm-svn: 135504
 2011-07-19 19:41:54 +00:00
Jim Grosbach
294b83e3e2 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
 2011-07-19 19:13:28 +00:00
Jim Grosbach
0789ef018d Whitespace. 
llvm-svn: 135499
 2011-07-19 19:02:39 +00:00
Jim Grosbach
14e26dd644 Remove unused code. 
cc_out and pred operands are added during parsing via custom C++ now.

llvm-svn: 135497
 2011-07-19 18:32:48 +00:00
Akira Hatanaka
19c16a84ff Fix comments. 
llvm-svn: 135496
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
f59cbeec14 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
57d207bc7b Separate code that modifies control flow from code that adds instruction to 
basic blocks.

llvm-svn: 135490
 2011-07-19 17:09:53 +00:00
Jim Grosbach
31cda4ed6d ARM range checking for so_imm operands in assembly parsing. 
llvm-svn: 135489
 2011-07-19 16:50:30 +00:00
Bob Wilson
7c9092c9aa Revert "Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block." 
This reverts commit 9fec5e346efdf744b151ae6604f912908315fa7a.

llvm-svn: 135486
 2011-07-19 16:32:50 +00:00
Bob Wilson
c7cb9841ca Revert "Update docs to reflect r135457." 
This reverts commit ba034c0a2e71303c7cf3f43ca8e69dc8436b32e2.

llvm-svn: 135485
 2011-07-19 16:31:58 +00:00
Jay Foad
6d007bef3c Convert ConstantFoldGetElementPtr to use ArrayRef. 
llvm-svn: 135483
 2011-07-19 15:30:30 +00:00
Jay Foad
bbbf29aab7 Convert SimplifyGEPInst to use ArrayRef. 
llvm-svn: 135482
 2011-07-19 15:07:52 +00:00
Jay Foad
83a0e1fa99 Convert gep_type_begin and gep_type_end to use ArrayRef. 
llvm-svn: 135481
 2011-07-19 14:42:50 +00:00
Jay Foad
0974b71f17 Convert TargetData::getIndexedOffset to use ArrayRef. 
llvm-svn: 135478
 2011-07-19 14:01:37 +00:00
Jay Foad
ae5894c5cc Use ArrayRef in ConstantFoldInstOperands and ConstantFoldCall. 
llvm-svn: 135477
 2011-07-19 13:32:40 +00:00
Richard Osborne
b469141419 Add intrinsics for the zext / sext instructions. 
llvm-svn: 135476
 2011-07-19 13:28:50 +00:00
Richard Osborne
50303e0d38 Add intrinsics for the testct, testwct instructions. 
llvm-svn: 135475
 2011-07-19 13:00:40 +00:00
Richard Osborne
409c0d7768 Add intrinsics for the peek and endin instructions. 
llvm-svn: 135474
 2011-07-19 12:50:25 +00:00
Nick Lewycky
7c36f4590e Remove bogus test: for all possible inputs of %X, the 'sub nsw' is guaranteed 
to perform a signed wrap. Don't rely on any particular handling of that case.

llvm-svn: 135471
 2011-07-19 08:22:57 +00:00
Evan Cheng
bfc0cac54d Introduce MCCodeGenInfo, which keeps information that can affect codegen 
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468
 2011-07-19 06:37:02 +00:00
Akira Hatanaka
ad3687eb3a Make EmitAtomic functions return the correct MachineBasicBlocks so that 
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465
 2011-07-19 03:42:13 +00:00
Akira Hatanaka
55b8d79a52 Do not insert instructions in reverse order. 
llvm-svn: 135464
 2011-07-19 03:14:58 +00:00
Eli Friedman
99b95e531f Make isLoadExtLegal and isTruncStoreLegal check what the name says. :) This might have some minor effect on CellSPU, but all other targets should be unaffected. Fixing per report from Damien Vincent on llvmdev. 
llvm-svn: 135462
 2011-07-19 02:24:07 +00:00
Devang Patel
d1cdabf6dc Update docs to reflect r135457. 
llvm-svn: 135458
 2011-07-19 01:04:39 +00:00
Devang Patel
e50d45c876 Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block. 
llvm-svn: 135457
 2011-07-19 01:03:32 +00:00
Devang Patel
72886ba8d8 Revert r135423. 
llvm-svn: 135454
 2011-07-19 00:28:24 +00:00
Jeffrey Yasskin
dd9a2cc0d2 Document how to maintain a git-svn clone of the LLVM git repositories. 
llvm-svn: 135453
 2011-07-19 00:20:54 +00:00
Bill Wendling
cd5cb5b44e Micro-opt: Only emit compact unwind if there is a compact unwind encoding to emit. 
llvm-svn: 135452
 2011-07-19 00:09:25 +00:00
Bill Wendling
8dd021da20 Use the CompactUnwindEncoding from the Frame, if it's defined. 
llvm-svn: 135451
 2011-07-19 00:06:12 +00:00
Bill Wendling
71a83a3b30 Add a frame with the compact unwind encoding if it exists. 
llvm-svn: 135450
 2011-07-19 00:02:51 +00:00
Bill Wendling
6211e2602f Add a method to set compact unwind encoding information in a frame. 
llvm-svn: 135449
 2011-07-19 00:01:42 +00:00
Bill Wendling
b1d5a0798a Rename CompactEncoding to CompactUnwindEncoding. 
llvm-svn: 135448
 2011-07-19 00:00:58 +00:00