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Author SHA1 Message Date
Chris Lattner
4c14d2c4a4 now that fp reg kill insertion stuff happens as a separate 
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.

llvm-svn: 104333
 2010-05-21 18:17:54 +00:00
Chris Lattner
1e1fb36df4 Use less evil form of switch stmt. 
llvm-svn: 104331
 2010-05-21 18:02:42 +00:00
Chris Lattner
8c562574eb use continue to reduce nesting. 
llvm-svn: 104330
 2010-05-21 18:01:24 +00:00
Chris Lattner
2077759153 pull a nested loop of this pass out to its own function, 
eliminating the gymnastics around the ContainsFPCode var.

llvm-svn: 104328
 2010-05-21 17:57:03 +00:00
Chris Lattner
91ffa7a5bf modernize this pass a bit, fit in 80 columns. 
llvm-svn: 104326
 2010-05-21 17:49:07 +00:00
Chris Lattner
1794093960 constify accessor. 
llvm-svn: 104325
 2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
a3cca88b41 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." 
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
 2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
edf8136011 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
924b84cf0f Teach VirtRegRewriter to handle spilling in instructions that have multiple 
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

llvm-svn: 104321
 2010-05-21 16:36:13 +00:00
Jakob Stoklund Olesen
6c22635216 If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
 2010-05-21 16:32:16 +00:00
Matt Fleming
5d40d53cab Currently, createMachOStreamer() is invoked directly in llvm-mc which 
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.

llvm-svn: 104318
 2010-05-21 12:54:43 +00:00
Matt Fleming
6a5cb8c84a Split out the x86_32 an x86_64 ELF backends as they handle ELF 
differently. This will make adding ELF support easier in the long run.

llvm-svn: 104317
 2010-05-21 11:39:07 +00:00
Matt Fleming
0ca99c0262 Add support for parsing the ELF .type assembler directive. 
llvm-svn: 104316
 2010-05-21 11:36:59 +00:00
Lang Hames
b579a16d82 Removed scaleNumbering method declaration from LiveInterval (not defined, not used). 
llvm-svn: 104311
 2010-05-21 03:04:04 +00:00
Dale Johannesen
d0a5fdb32f Fix i64->f64 conversion, x86-64, -no-sse. A bit 
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.

llvm-svn: 104308
 2010-05-21 00:52:33 +00:00
Evan Cheng
6397a77e16 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
llvm-svn: 104307
 2010-05-21 00:43:17 +00:00
Evan Cheng
1faccbd51a Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid. 
llvm-svn: 104306
 2010-05-21 00:42:32 +00:00
Daniel Dunbar
8824824171 Remove dead option. 
llvm-svn: 104303
 2010-05-21 00:27:55 +00:00
Devang Patel
765d605934 Simplify. 
llvm-svn: 104302
 2010-05-21 00:10:20 +00:00
Daniel Dunbar
38460e2596 Fix __crashreport_info__ declaration. 
llvm-svn: 104300
 2010-05-20 23:50:19 +00:00
Evan Cheng
b5de7de4ce Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
llvm-svn: 104293
 2010-05-20 23:26:43 +00:00
Dan Gohman
3274120902 DominatorTree.getNode can return null for unreachable blocks. 
llvm-svn: 104290
 2010-05-20 22:46:54 +00:00
Dan Gohman
b841e5c433 Minor code cleanups. 
llvm-svn: 104287
 2010-05-20 22:25:20 +00:00
Mikhail Glushenkov
5ead1e50a7 Print a space after the colon. 
llvm-svn: 104279
 2010-05-20 21:11:37 +00:00
Dan Gohman
06b35689ec Make Solve check its own post-condition, to reduce clutter in the 
top-level LSRInstance logic.

llvm-svn: 104278
 2010-05-20 20:59:23 +00:00
Dan Gohman
2702e3105d Add comments. 
llvm-svn: 104276
 2010-05-20 20:52:00 +00:00
Daniel Dunbar
3a0c98ca87 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
llvm-svn: 104275
 2010-05-20 20:36:29 +00:00
Devang Patel
3d4cd812aa Rename variable. add comment. 
llvm-svn: 104274
 2010-05-20 20:35:24 +00:00
Dan Gohman
5f16e1b2cb More code cleanups. Use iterators instead of indices when indices 
aren't needed.

llvm-svn: 104273
 2010-05-20 20:33:18 +00:00
Daniel Dunbar
030b1001c0 X86: Model i64i32imm properly, as a subclass of all immediates. 
llvm-svn: 104272
 2010-05-20 20:20:39 +00:00
Daniel Dunbar
6cbde7d71e X86: Fix immediate type of FOO64i32 operations. 
llvm-svn: 104271
 2010-05-20 20:20:35 +00:00
Daniel Dunbar
64807873ec tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor 
it.

llvm-svn: 104270
 2010-05-20 20:20:32 +00:00
Dan Gohman
aa116e0758 Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set 
Changed directly instead of using a return value.

Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.

llvm-svn: 104269
 2010-05-20 20:05:31 +00:00
Dan Gohman
ad77b290d0 Add some comments. 
llvm-svn: 104268
 2010-05-20 20:00:41 +00:00
Dan Gohman
b08c4f5ab9 Simplify this code. Don't do a DomTreeNode lookup for each visited block. 
llvm-svn: 104267
 2010-05-20 20:00:25 +00:00
Devang Patel
32a1ce3b3a Refactor. 
llvm-svn: 104265
 2010-05-20 19:57:06 +00:00
Matt Fleming
eb6f789e6f Grammar fix. This is a test commit. 
llvm-svn: 104264
 2010-05-20 19:45:09 +00:00
Dan Gohman
86f6190fc2 Minor code cleanups. 
llvm-svn: 104263
 2010-05-20 19:44:23 +00:00
Dan Gohman
89f64e13fe When canonicalizing icmp operand order to put the loop invariant 
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.

Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.

llvm-svn: 104262
 2010-05-20 19:26:52 +00:00
Mikhail Glushenkov
ed1c9f41bf llvmc: Make segfault detection work on Win32. 
llvm-svn: 104261
 2010-05-20 19:23:47 +00:00
Dan Gohman
75ee6c3611 Set Changed to true when canonicalizing ICmp operand order; even though 
it isn't a very interesting change, it's a change nonetheless.

llvm-svn: 104260
 2010-05-20 19:16:03 +00:00
Bob Wilson
11aebf39f1 Handle Neon v2f64 and v2i64 vector shuffles as register copies. 
This fixes the remaining issue with pr7167.

llvm-svn: 104257
 2010-05-20 18:39:53 +00:00
Jim Grosbach
5029c599b3 Remove dbg_value workaround and associated command line option 
llvm-svn: 104254
 2010-05-20 18:34:01 +00:00
Dan Gohman
7dcd59b8b2 Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't 
have a pattern and it had an invalid encoding.

llvm-svn: 104244
 2010-05-20 18:05:01 +00:00
Dale Johannesen
78714b5dc9 The PPC MFCR instruction implicitly uses all 8 of the CR 
registers.  Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
 vreg = MCRF  CR0
 MFCR  <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment).  That avoids all problems.  7739628.

llvm-svn: 104238
 2010-05-20 17:48:26 +00:00
Devang Patel
ae24244a10 Strip llvm.dbg.lv also. 
llvm-svn: 104236
 2010-05-20 16:49:22 +00:00
Dan Gohman
af66103d32 Rename a variable to avoid shadowing. 
llvm-svn: 104234
 2010-05-20 16:41:11 +00:00
Devang Patel
f90f78669f Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label. 
llvm-svn: 104233
 2010-05-20 16:36:41 +00:00
Dan Gohman
db5be4dfc7 Minor code simplification. 
llvm-svn: 104232
 2010-05-20 16:23:28 +00:00
Dan Gohman
c8b4555a94 Fix assembly parsing and encoding of the pushf and popf family of 
instructions.

llvm-svn: 104231
 2010-05-20 16:16:00 +00:00