Jim Grosbach
9e5ef02adb
ARM add more 'gas' compatibility aliases for NEON instructions.
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llvm-svn: 146507
2011-12-13 20:08:32 +00:00
Jim Grosbach
a33fa8aa88
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach
a740cc6bc9
ARM tidy up and remove no longer needed InstAlias definitions.
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The TokenAlias handling of data type suffices renders these unnecessary.
llvm-svn: 146010
2011-12-07 01:50:36 +00:00
Jim Grosbach
19d37b966b
ARM Implement ARM ARM Table A7-3 via TokenAlias.
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Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.
rdar://10435076
llvm-svn: 146007
2011-12-07 01:17:58 +00:00
Jim Grosbach
9c017fb254
ARM assembly parsing for the rest of the VMUL data type aliases.
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Finish up rdar://10522016.
llvm-svn: 145846
2011-12-05 20:29:59 +00:00
Jim Grosbach
7b62c2f71d
ARM assmebler parsing for two-operand VMUL instructions.
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Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.
rdar://10522016
llvm-svn: 145842
2011-12-05 19:55:46 +00:00
Jim Grosbach
82ae7f46ea
ARM VLD1 single lane assembly parsing.
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llvm-svn: 145712
2011-12-02 22:01:52 +00:00
Jim Grosbach
a568ef0db6
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
Jim Grosbach
778bed02bb
ARM assembly parsing for data type suffices on NEON VMOV aliases.
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llvm-svn: 144722
2011-11-15 22:54:42 +00:00
Jim Grosbach
1d07736422
Split out the plain '.{8|16|32|64}' suffix handling.
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Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.
llvm-svn: 144588
2011-11-14 23:20:14 +00:00
Jim Grosbach
00283a5c8e
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
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rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
Jim Grosbach
4a2f107b04
ARM VLDR/VSTR instructions don't need a size suffix.
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Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
Jim Grosbach
009733c9e4
ARM assembly parsing type suffix options for VLDR/VSTR.
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rdar://10435076
llvm-svn: 144575
2011-11-14 22:28:39 +00:00
Jim Grosbach
7e41554aa7
ARM refactor simple immediate asm operand render methods.
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These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
llvm-svn: 144439
2011-11-12 00:58:43 +00:00
Jim Grosbach
b66dfc2999
ARM assembly parsing for ASR(immediate).
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Start of rdar://9704684
llvm-svn: 144293
2011-11-10 16:44:55 +00:00
Jim Grosbach
c5f44d0b71
ARM VLD/VST assembly parsing for symbolic address operands.
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llvm-svn: 143413
2011-11-01 01:24:45 +00:00
Owen Anderson
3dd6c949a5
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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llvm-svn: 143208
2011-10-28 18:02:13 +00:00
Jim Grosbach
94980a23e6
ARM NEON assembly parsing and encoding for VDUP(scalar).
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llvm-svn: 141446
2011-10-07 23:56:00 +00:00
Jim Grosbach
21a9f8f50f
ARM assembly parsing and encoding for VMRS/FMSTAT.
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llvm-svn: 141025
2011-10-03 21:12:43 +00:00
Owen Anderson
05ef2c122d
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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llvm-svn: 139522
2011-09-12 18:56:30 +00:00
Jim Grosbach
9f150bfedf
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
Jim Grosbach
5ac3aa158b
Thumb2 assembly parsing and encoding for LDR post-indexed.
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More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
llvm-svn: 139272
2011-09-08 01:01:32 +00:00
Jim Grosbach
1aa191032a
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
...
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
llvm-svn: 139270
2011-09-08 00:39:19 +00:00
Owen Anderson
4ae835d7c9
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
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llvm-svn: 138339
2011-08-23 17:45:18 +00:00
Owen Anderson
33f3f4ec2a
Reject invalid imod values in t2CPS instructions.
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llvm-svn: 138306
2011-08-22 23:44:04 +00:00
Jim Grosbach
a5715c60b5
Clean up predicates on ARM target instruction aliases.
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llvm-svn: 138249
2011-08-22 18:04:24 +00:00
Jim Grosbach
cf35d78b16
Thumb assembly parsing and encoding for MOV.
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llvm-svn: 138076
2011-08-19 20:46:54 +00:00
Jim Grosbach
8952a2e87e
Tidy up. Tab character.
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llvm-svn: 138072
2011-08-19 20:30:19 +00:00
Jim Grosbach
8e03b52754
Tab characters.
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llvm-svn: 138066
2011-08-19 19:41:46 +00:00
Owen Anderson
ffb049d199
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
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llvm-svn: 137787
2011-08-16 23:45:44 +00:00
Jim Grosbach
8d67a0e07c
ARM thumb assembly parsing for arithmetic flag setting instructions.
...
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
llvm-svn: 137746
2011-08-16 20:45:50 +00:00
Owen Anderson
2e722e7cd4
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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llvm-svn: 137686
2011-08-15 23:38:54 +00:00
Owen Anderson
f86afc2459
Remove dead classes.
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llvm-svn: 137643
2011-08-15 20:11:11 +00:00
Jim Grosbach
b2b673661a
Update comment to reflect MC target machine refactor.
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llvm-svn: 137615
2011-08-15 16:52:24 +00:00
Owen Anderson
7b426d97ad
Fix decoding of ARM-mode STRH.
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llvm-svn: 137499
2011-08-12 20:02:50 +00:00
Jim Grosbach
15351f4f22
Tidy up. Remove unused template parameter.
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llvm-svn: 137345
2011-08-11 20:41:13 +00:00
Jim Grosbach
81b2835f83
ARM STRD assembly parsing and encoding.
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llvm-svn: 137342
2011-08-11 20:28:23 +00:00
Owen Anderson
73e7d34732
Continue to tighten decoding by performing more operand validation.
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llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Owen Anderson
0fde7a84ee
Add initial support for decoding NEON instructions in Thumb2 mode.
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llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson
ffe1c55752
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
...
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Owen Anderson
11e2000c8c
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
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llvm-svn: 136942
2011-08-04 23:18:05 +00:00
Jim Grosbach
767e9d16e6
ARM refactoring assembly parsing of memory address operands.
...
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Owen Anderson
cc4c746c65
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
...
llvm-svn: 136141
2011-07-26 20:54:26 +00:00
Jim Grosbach
4681ef2468
ARM fix for LDREX source register encoding.
...
rdar://9842203
llvm-svn: 136102
2011-07-26 17:44:46 +00:00
Jim Grosbach
6fbee17fef
ARM assembly parsing and encoding for SWP[B] instructions.
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llvm-svn: 136098
2011-07-26 17:15:11 +00:00
Jim Grosbach
3cd3217e6c
Clean up the ARM asm parser a bit.
...
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.
llvm-svn: 136095
2011-07-26 17:10:22 +00:00
Jim Grosbach
07bb1d91c0
More simple cleanup of ARM asm operand definitions.
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llvm-svn: 135958
2011-07-25 20:38:18 +00:00
Jim Grosbach
f45795436a
Make assembly parser method names more consistent.
...
llvm-svn: 135950
2011-07-25 20:14:50 +00:00
Jim Grosbach
0fe45ec0ed
ARM assembly parsing and encoding for SETEND instruction.
...
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
llvm-svn: 135776
2011-07-22 17:44:50 +00:00
Owen Anderson
e34471d064
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
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llvm-svn: 135722
2011-07-21 23:38:37 +00:00