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96619 Commits

Author SHA1 Message Date
Hans Wennborg
b90166e9d0 vs2013 msbuild integration: add missing .target files, fix typo in CMakeLists
This should fix PR17568.

Patch by Josh Samuel!

llvm-svn: 192610
2013-10-14 18:16:37 +00:00
Will Dietz
ad27c13a64 MachineSink: Fix and tweak critical-edge breaking heuristic.
Per original comment, the intention of this loop
is to go ahead and break the critical edge
(in order to sink this instruction) if there's
reason to believe doing so might "unblock" the
sinking of additional instructions that define
registers used by this one.  The idea is that if
we have a few instructions to sink "together"
breaking the edge might be worthwhile.

This commit makes a few small changes
to help better realize this goal:

First, modify the loop to ignore registers
defined by this instruction.  We don't
sink definitions of physical registers,
and sinking an SSA definition isn't
going to unblock an upstream instruction.

Second, ignore uses of physical registers.
Instructions that define physical registers are
rejected for sinking, and so moving this one
won't enable moving any defining instructions.
As an added bonus, while virtual register
use-def chains are generally small due
to SSA goodness, iteration over the uses
and definitions (used by hasOneNonDBGUse)
for physical registers like EFLAGS
can be rather expensive in practice.
(This is the original reason for looking at this)

Finally, to keep things simple continue
to only consider this trick for registers that
have a single use (via hasOneNonDBGUse),
but to avoid spuriously breaking critical edges
only do so if the definition resides
in the same MBB and therefore this one directly
blocks it from being sunk as well.
If sinking them together is meant to be,
let the iterative nature of this pass
sink the definition into this block first.

Update tests to accomodate this change,
add new testcase where sinking avoids pipeline stalls.

llvm-svn: 192608
2013-10-14 16:57:17 +00:00
Rafael Espindola
4db95cc6d9 Remove utils/profile.pl.
It uses now removed opt options.

Patch by Alastair Murray!

llvm-svn: 192606
2013-10-14 16:48:32 +00:00
Rafael Espindola
d9b08f1296 Remove lib/Transforms/Instrumentation/ProfilingUtils.*
They were leftover from the old profiling support.

Patch by Alastair Murray.

llvm-svn: 192605
2013-10-14 16:46:46 +00:00
Rafael Espindola
0ee3f8f595 Remove the now unused strong phi elimination pass.
llvm-svn: 192604
2013-10-14 16:39:04 +00:00
Chris Lattner
18bf2f7f32 Basic blocks typically have few predecessors. Use a SmallDenseMap to
avoid a heap allocation when this is the case.

llvm-svn: 192602
2013-10-14 16:05:55 +00:00
Evgeniy Stepanov
bd5e5ef8a1 [msan] Instrument x86.*_cvt* intrinsics.
Currently MSan checks that arguments of *cvt* intrinsics are fully initialized.
That's too much to ask: some of them only operate on lower half, or even
quarter, of the input register.

llvm-svn: 192599
2013-10-14 15:16:25 +00:00
Chad Rosier
40761dc629 [AArch64] Add support for NEON scalar integer compare instructions.
llvm-svn: 192596
2013-10-14 14:37:20 +00:00
Bernard Ogden
f482ee15d7 Add Cortex-A57 support
llvm-svn: 192591
2013-10-14 13:17:07 +00:00
Bernard Ogden
ec0167a2ce Add subtarget feature support for Cortex-A53
Some previous implicit defaults have changed, for example FP and NEON
are now on by default.

llvm-svn: 192590
2013-10-14 13:16:57 +00:00
Matheus Almeida
ddef49ec19 [mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}

llvm-svn: 192589
2013-10-14 13:07:39 +00:00
Matheus Almeida
7f2a89252c [mips][msa] Direct Object Emission support for VEC instructions.
List of instructions:
and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v.

llvm-svn: 192588
2013-10-14 12:57:18 +00:00
Matheus Almeida
8228438976 [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.
llvm-svn: 192587
2013-10-14 12:38:17 +00:00
Matheus Almeida
20c2576009 [mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}

llvm-svn: 192586
2013-10-14 12:22:43 +00:00
Matheus Almeida
467e191e55 [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.
INSERT is the first type of MSA instruction that requires a change to the way
MSA registers are parsed. This happens because MSA registers may be suffixed by
an index in the form of an immediate or a general purpose register. The changes
to parseMSARegs reflect that requirement.

llvm-svn: 192582
2013-10-14 11:49:30 +00:00
Evgeniy Stepanov
57dafd2630 [msan] Fix handling of scalar select of vectors.
llvm-svn: 192575
2013-10-14 09:52:09 +00:00
Elena Demikhovsky
c460e7e50a Fixed a bug in dynamic allocation memory on stack.
The alignment of allocated space was wrong, see Bugzila 17345.

Done by Zvi Rackover <zvi.rackover@intel.com>.

llvm-svn: 192573
2013-10-14 07:26:51 +00:00
Craig Topper
fe4fce729c Create classes to reduce the size of the tablegen entries for the CRC32 instructions.
llvm-svn: 192568
2013-10-14 05:19:58 +00:00
Craig Topper
1548551887 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.
llvm-svn: 192567
2013-10-14 04:55:01 +00:00
Craig Topper
ba1540e28a Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
llvm-svn: 192566
2013-10-14 01:42:32 +00:00
Craig Topper
c9050b2d46 Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
llvm-svn: 192565
2013-10-14 01:21:22 +00:00
David Majnemer
09abde1f56 Windows: Fix a typo in an assert
llvm-svn: 192564
2013-10-14 01:17:32 +00:00
Craig Topper
bb1360277e Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions.
llvm-svn: 192562
2013-10-14 00:24:33 +00:00
David Majnemer
4d71e79ad9 Windows: Don't bother with pinning Kernel32.dll
We don't delay load it so it shouldn't be going anywhere.

llvm-svn: 192561
2013-10-14 00:06:58 +00:00
Will Dietz
ba9279f9d8 MC: Don't assume incoming StringRef's are null terminated.
This can happen when processing command line arguments, which
are often stored as std::string's and later turned into
StringRef's via std::string::data().  Unfortunately this
is not guaranteed to return a null-terminated string
until C++11, causing breakage on platforms that don't do this.

llvm-svn: 192558
2013-10-13 22:09:26 +00:00
Vincent Lejeune
7594bd2071 R600: improve dump of S_WAITCNT
llvm-svn: 192557
2013-10-13 17:56:28 +00:00
Vincent Lejeune
f5655b2100 R600/SI: Add SinkingPass before ISel
llvm-svn: 192556
2013-10-13 17:56:21 +00:00
Vincent Lejeune
177a4d2fce R600/SI: Support byval arguments
llvm-svn: 192555
2013-10-13 17:56:16 +00:00
Vincent Lejeune
316b632e03 R600: Use masked read sel for texture instructions
llvm-svn: 192554
2013-10-13 17:56:10 +00:00
Vincent Lejeune
b337ac16bc R600: fix swizzle export
llvm-svn: 192553
2013-10-13 17:56:04 +00:00
Vincent Lejeune
01edfbbc81 R600: Clear the VPM bit of export instructions.
It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

llvm-svn: 192552
2013-10-13 17:55:57 +00:00
David Majnemer
c42176a26f Windows: Use GetModuleHandleEx instead of LoadLibrary
We were using an anti-pattern of:
 - LoadLibrary
 - GetProcAddress
 - FreeLibrary

This is problematic because of several reasons:
 - We are holding on to pointers into a library we just unloaded.
 - Calling LoadLibrary results in an increase in the reference count of
   the library in question and any libraries that it depends on and
   so-on and so-forth.  This is none too quick.

Instead, use GetModuleHandleEx with GET_MODULE_HANDLE_EX_FLAG_PIN.  This
is done because because we didn't bring the reference for the library
into existence and therefor shouldn't count on it being around later.

llvm-svn: 192550
2013-10-13 10:34:21 +00:00
Will Dietz
1aec30eefe TargetLowering: Don't index into empty string.
(This is triggered by current lit tests)

llvm-svn: 192549
2013-10-13 03:08:49 +00:00
Will Dietz
be3a7e9197 yaml2coff/elf: Touchup for compatibility.
* std::string::append(int, int) can be ambiguous.
* std::vector<>::data() is a C++11 feature, use ArrayRef abstraction.

llvm-svn: 192542
2013-10-12 21:29:16 +00:00
Arnold Schwaighofer
38ec37faba SLPVectorizer: Sort PHINodes based on their opcode
Before this patch we relied on the order of phi nodes when we looked for phi
nodes of the same type. This could prevent vectorization of cases where there
was a phi node of a second type in between phi nodes of some type.

This is important for vectorization of an internal graphics kernel. On the test
suite + external on x86_64 (and on a run on armv7s) it showed no impact on
either performance or compile time.

radar://15024459

llvm-svn: 192537
2013-10-12 18:56:27 +00:00
Tobias Grosser
bc154d94d0 LoopVectorize: Add missing INITIALIZE_PASS_DEPENDENCY macros
Contributed-by:  Peter Zotov  <whitequark@whitequark.org>
llvm-svn: 192536
2013-10-12 18:29:15 +00:00
Benjamin Kramer
3000b81f9a Force a CPU on test so it doesn't depend on microarchitectural scheduling decisions.
llvm-svn: 192532
2013-10-12 11:17:12 +00:00
Bill Wendling
3f4435b611 Update so that it uses the `-V' command line option and supports Python 3.x.
llvm-svn: 192527
2013-10-12 08:42:59 +00:00
Craig Topper
47d75426b9 Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
llvm-svn: 192525
2013-10-12 05:41:08 +00:00
Tom Stellard
a496e8729f R600: Store disassembly in a special ELF section when feature +DumpCode is enabled.
Patch by: Jay Cornwall

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 192523
2013-10-12 05:02:51 +00:00
Craig Topper
1e89b25474 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler.
llvm-svn: 192522
2013-10-12 04:46:18 +00:00
Reed Kotler
9efb450361 For Mips16, start to consolidate all forms of 32 bit literal loading so that
they can be better handled and optimized in the Mips16 constant island code.

llvm-svn: 192520
2013-10-12 02:19:08 +00:00
Will Dietz
2703980be5 Add missing #include's to cctype when using isdigit/alpha/etc.
llvm-svn: 192519
2013-10-12 00:55:57 +00:00
Manman Ren
7a7dcac18c Debug Info: remove form from function addDIEEntry.
The form must be a reference form in addDIEEntry. Which reference form to
use will be decided by the callee.

No functionality change.

llvm-svn: 192517
2013-10-11 23:58:05 +00:00
Andrew Kaylor
54a20b979d Fixing problems in lli's RemoteMemoryManager.
This fixes a problem from a previous check-in where a return value was omitted.

Previously the remote/stubs-remote.ll and remote/stubs-sm-pic.ll tests were reporting passes, but they should have been failing.  Those tests attempt to link against an external symbol and remote symbol resolution is not supported.  The old RemoteMemoryManager implementation resulted in local symbols being used for resolution and the child process crashed but the test didn't notice.  With this check-in remote symbol resolution fails, and so the test (correctly) fails.

llvm-svn: 192514
2013-10-11 22:47:10 +00:00
Andrew Kaylor
0f28749d52 Adding multiple object support to MCJIT EH frame handling
llvm-svn: 192504
2013-10-11 21:25:48 +00:00
Matt Arsenault
289accc07f R600: Add scalar i32 add test
llvm-svn: 192501
2013-10-11 21:03:41 +00:00
Matt Arsenault
d5c3e13cc5 Use CHECK-LABEL
llvm-svn: 192500
2013-10-11 21:03:39 +00:00
Matt Arsenault
7dd90a7b4d Fix typo
llvm-svn: 192499
2013-10-11 21:03:36 +00:00
Benjamin Kramer
4742b4b956 fConversion: Attempt #2 at fixing the MSVC build.
llvm-svn: 192492
2013-10-11 19:49:09 +00:00