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65 Commits

Author SHA1 Message Date
Craig Topper
f34a1d74e9 [X86] Remove many operands that represent memory stores from outs to ins. These operands are the registers and immediates that specify the memory address not the memory itself thus they are inputs. 
llvm-svn: 263354
 2016-03-13 02:56:31 +00:00
Craig Topper
6dd1abcce8 [X86] Mark LDS/LES as not being allowed in 64-bit mode. 
Their opcodes are used as part of the VEX prefix in 64-bit mode. Clearly the disassembler implicitly decoded them as AVX instructions in 64-bit mode, but I think the AsmParser would have encoded them.

llvm-svn: 258793
 2016-01-26 06:10:15 +00:00
Craig Topper
f0f0ca85b5 [X86] Use PS instead of TB for instructions that have PD/XS/XD variations. Use OpSize32 on an instruction that has an OpSize16 variant. 
llvm-svn: 256918
 2016-01-06 06:18:41 +00:00
Asaf Badouh
f9720f53b4 [X86][PKU] Add {RD,WR}PKRU intrinsics 
Differential Revision: http://reviews.llvm.org/D15808

llvm-svn: 256670
 2015-12-31 08:31:13 +00:00
Asaf Badouh
593a27ca5c [X86][PKU] Add {RD,WR}PKRU encoding 
Differential Revision: http://reviews.llvm.org/D15711

llvm-svn: 256366
 2015-12-24 08:25:00 +00:00
Amjad Aboud
8197f10787 Implemented Support of IA interrupt and exception handlers: 
http://lists.llvm.org/pipermail/cfe-dev/2015-September/045171.html

Differential Revision: http://reviews.llvm.org/D15567

llvm-svn: 256155
 2015-12-21 14:07:14 +00:00
Amjad Aboud
7b91f508e9 [X86] Add XSAVE intrinsic family 
Add intrinsics for the
  XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64)
  XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64)
  XSAVEC instructions (XSAVEC/XSAVEC64)
  XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64)

Differential Revision: http://reviews.llvm.org/D13012

llvm-svn: 250029
 2015-10-12 11:47:46 +00:00
Craig Topper
18c728de25 [X86] Change the immediate for IN/OUT instructions to u8imm so the assembly parser will check the size. 
llvm-svn: 250012
 2015-10-12 04:17:55 +00:00
Craig Topper
7a2aafba5d [X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior. 
This also fixes a bug where negative immediates below -128 were not being reported as errors.

llvm-svn: 249989
 2015-10-11 18:27:24 +00:00
Craig Topper
55bddcfc08 [X86] Add register use/def for wrmsr and rdmsr. 
llvm-svn: 228515
 2015-02-07 23:36:51 +00:00
Craig Topper
0fbb3fa6e9 [X86] Add GETSEC instruction. 
llvm-svn: 228514
 2015-02-07 23:36:36 +00:00
Craig Topper
e2e6d72938 [X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions 
llvm-svn: 228283
 2015-02-05 08:51:06 +00:00
Craig Topper
11f57fde4f [X86] Remove two feature flags that covered sets of instructions that have no patterns or intrinsics. Since we don't check feature flags in the assembler parser for any instruction sets, these flags don't provide any value. This frees up 2 of the fully utilized feature flags. 
llvm-svn: 228282
 2015-02-05 08:51:02 +00:00
Craig Topper
5a9b4168e7 [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. 
llvm-svn: 227963
 2015-02-03 11:03:57 +00:00
Alex Rosenberg
6b9851d1e6 Use a different encoding for debugtrap on PS4. 
llvm-svn: 227116
 2015-01-26 19:09:27 +00:00
Michael Liao
59822d4755 [X86] Clean up whitespace as well as minor coding style 
llvm-svn: 223339
 2014-12-04 05:20:33 +00:00
Reid Kleckner
9948800a98 X86: cpuid and xgetbv write to 32-bit registers, not 64-bit 
This fixes an issue where MS inline assembly containing xgetbv wouldn't
be marked as clobbering EAX:EDX. Test for that forthcoming on the Clang
side.

llvm-svn: 217173
 2014-09-04 16:58:25 +00:00
Robert Khasanov
350e87272b [x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes 
llvm-svn: 216163
 2014-08-21 09:34:12 +00:00
Andrea Di Biagio
2bc066b1b4 [X86] Add support for builtin to read performance monitoring counters. 
This patch adds support for a new builtin instruction called
__builtin_ia32_rdpmc.

Builtin '__builtin_ia32_rdpmc' is defined as a 'GCC builtin'; on X86, it can
be used to read performance monitoring counters. It takes as input the index
of the performance counter to read, and returns the value of the specified
performance counter as a 64-bit number.

Calls to this new builtin will map to instruction RDPMC.
The index in input to the builtin call is moved to register %ECX. The result
of the builtin call is the value of the specified performance counter (RDPMC
would return that quantity in registers RDX:RAX).

This patch:
 - Adds builtin int_x86_rdpmc as a GCCBuiltin;
 - Adds a new x86 DAG node called 'RDPMC_DAG';
 - Teaches how to lower this new builtin;
 - Adds an ISel pattern to select instruction RDPMC;
 - Fixes the definition of instruction RDPMC adding %RAX and %RDX as
   implicit definitions, and adding %ECX as implicit use;
 - Adds a LLVM test to verify that the new builtin is correctly selected.

llvm-svn: 212049
 2014-06-30 17:14:21 +00:00
Andrea Di Biagio
dae3a5b91a [X86] Add support for Read Time Stamp Counter x86 builtin intrinsics. 
This patch:
- Adds two new X86 builtin intrinsics ('int_x86_rdtsc' and
   'int_x86_rdtscp') as GCCBuiltin intrinsics;
- Teaches the backend how to lower the two new builtins;
- Introduces a common function to lower READCYCLECOUNTER dag nodes
  and the two new rdtsc/rdtscp intrinsics;
- Improves (and extends) the existing x86 test 'rdtsc.ll'; now test 'rdtsc.ll'
  correctly verifies that both READCYCLECOUNTER and the two new intrinsics
  work fine for both 64bit and 32bit Subtargets.

llvm-svn: 207127
 2014-04-24 17:18:27 +00:00
Craig Topper
6d9ad3a694 [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS 
llvm-svn: 202348
 2014-02-27 05:08:25 +00:00
Craig Topper
ab427284c0 [x86] Add same itinerary to SYSEXIT64 as SYSEXIT for consistency. 
llvm-svn: 202240
 2014-02-26 06:50:27 +00:00
Craig Topper
5b20c52fcc Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 
llvm-svn: 201641
 2014-02-19 05:34:21 +00:00
Craig Topper
b5b81fb98b Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction. 
llvm-svn: 201550
 2014-02-18 08:18:29 +00:00
Craig Topper
e916566881 Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. 
llvm-svn: 200626
 2014-02-02 09:25:09 +00:00
Craig Topper
f97f309449 Simplify some x86 format classes and remove some ambiguities in their application. 
llvm-svn: 200608
 2014-02-01 08:17:56 +00:00
Reid Kleckner
3e9723ef68 x86: add implicit defs for cpuid 
This avoids miscompiling MS inline asm in LLVM where we have to infer
clobbers.  Test case forthcoming in Clang.

llvm-svn: 200279
 2014-01-28 02:08:22 +00:00
David Woodhouse
fa88b9de95 [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385) 
llvm-svn: 199809
 2014-01-22 15:08:55 +00:00
Craig Topper
af93615a67 Switch a few instructions to use RI instead I so they don't require REX_W to be explicitly specified. 
llvm-svn: 199479
 2014-01-17 08:16:57 +00:00
Craig Topper
1c1ecbff81 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.

llvm-svn: 199193
 2014-01-14 07:41:20 +00:00
David Woodhouse
7d0744dadf [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases 
llvm-svn: 198755
 2014-01-08 12:57:55 +00:00
David Woodhouse
8bc826fd14 [x86] Add OpSize16 to instructions that need it 
This fixes the bulk of 16-bit output, and the corresponding test case
x86-16.s now looks mostly like the x86-32.s test case that it was
originally based on. A few irrelevant instructions have been dropped,
and there are still some corner cases to be fixed in subsequent patches.

llvm-svn: 198752
 2014-01-08 12:57:40 +00:00
Craig Topper
0418d1dd5a Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
llvm-svn: 198515
 2014-01-04 22:29:41 +00:00
Craig Topper
ba17ca1e89 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
llvm-svn: 198327
 2014-01-02 18:20:48 +00:00
Eric Christopher
24d8bb6edd [x86] Rename In32BitMode predicate to Not64BitMode 
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

llvm-svn: 197768
 2013-12-20 02:04:49 +00:00
Craig Topper
45e8fdfc7f Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. 
Patch by Richard Mitton.

llvm-svn: 187476
 2013-07-31 02:47:52 +00:00
Michael Liao
75c886a312 Add CLAC/STAC instruction encoding/decoding support 
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.

llvm-svn: 179266
 2013-04-11 04:52:28 +00:00
Kay Tiong Khoo
5f12d15d44 fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases 
llvm-svn: 179223
 2013-04-10 21:52:25 +00:00
Kay Tiong Khoo
ba75929324 fixed to disassemble with tab after mnemonic rather than space 
llvm-svn: 179215
 2013-04-10 21:17:58 +00:00
Jakob Stoklund Olesen
042f102514 Add a catch-all WriteSystem SchedWrite type. 
This is used for all the expensive system instructions.

llvm-svn: 177598
 2013-03-20 23:09:50 +00:00
Kay Tiong Khoo
09400e6c4a *fixed disassembly of some i386 system insts with intel syntax 
*added file for test cases for i386 intel syntax

llvm-svn: 174900
 2013-02-11 19:46:36 +00:00
Dan Gohman
cc1f60a86c Rename @llvm.debugger to @llvm.debugtrap. 
llvm-svn: 156774
 2012-05-14 18:58:10 +00:00
Dan Gohman
ed475ad173 Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(), 
but it generates int3 on x86 instead of ud2.

llvm-svn: 156593
 2012-05-11 00:19:32 +00:00
Preston Gurd
8de39bd4f6 Adds Intel Atom scheduling latencies to X86InstrSystem.td. 
llvm-svn: 156194
 2012-05-04 19:26:37 +00:00
Bill Wendling
1a3f2619a7 Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax. 
Patch by Kay Tiong Khoo!

llvm-svn: 152487
 2012-03-10 07:37:27 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Devang Patel
88a31798bc Fix asm string wrt variants. 
llvm-svn: 147805
 2012-01-09 21:32:02 +00:00
Craig Topper
f2a9bd3a4a Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. 
llvm-svn: 143319
 2011-10-30 19:57:21 +00:00
Kevin Enderby
837c1d56a2 Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and 
not depend on In32BitMode.  Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode.  rdar://9738584

llvm-svn: 143112
 2011-10-27 17:40:41 +00:00
Craig Topper
91b4292682 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
llvm-svn: 142117
 2011-10-16 07:05:40 +00:00