Evan Cheng
a2eaed93a0
INC / DEC instructions have shorter code size than ADD32ri8, etc.
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llvm-svn: 29194
2006-07-19 00:27:29 +00:00
Evan Cheng
dc9b5f5fc0
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
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llvm-svn: 28324
2006-05-16 07:21:53 +00:00
Evan Cheng
8768f25c80
SSE / SSE2 conversion intrinsics.
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llvm-svn: 27637
2006-04-12 23:42:44 +00:00
Evan Cheng
798acd4094
movnt* and maskmovdqu intrinsics
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llvm-svn: 27587
2006-04-11 06:57:30 +00:00
Evan Cheng
cad90504fe
Instruction encoding bug
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llvm-svn: 27102
2006-03-25 06:00:03 +00:00
Evan Cheng
b280b34497
Added CVTTPS2PI.
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llvm-svn: 27095
2006-03-25 01:31:59 +00:00
Evan Cheng
7c8d7bc4b3
Didn't mean to check this in. No MMX support yet.
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llvm-svn: 26933
2006-03-21 23:04:23 +00:00
Evan Cheng
47dd756c72
- Use movaps to store 128-bit vector integers.
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- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.
llvm-svn: 26932
2006-03-21 23:01:21 +00:00
Evan Cheng
6ec225863c
- Remove scalar to vector pseudo ops. They are just wrong.
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- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.
llvm-svn: 26919
2006-03-21 07:09:35 +00:00
Evan Cheng
a4db61ddc1
x86 ISD::SCALAR_TO_VECTOR support.
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llvm-svn: 26911
2006-03-21 00:33:35 +00:00
Evan Cheng
c63d434203
Move a few things around.
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llvm-svn: 26893
2006-03-20 06:04:52 +00:00
Evan Cheng
8ab6294f94
One more round of reorg so sabre doesn't freak out. :-)
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llvm-svn: 26303
2006-02-21 20:00:20 +00:00
Evan Cheng
fee17dfff8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
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llvm-svn: 26300
2006-02-21 19:13:53 +00:00
