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Commit Graph

145819 Commits

Author SHA1 Message Date
Peter Collingbourne
85c3314674 WholeProgramDevirt: Add any unsuccessful llvm.type.checked.load devirtualizations to the list of llvm.type.test users.
Any unsuccessful llvm.type.checked.load devirtualizations will be translated
into uses of llvm.type.test, so we need to add the resulting llvm.type.test
intrinsics to the function summaries so that the LowerTypeTests pass will
export them.

Differential Revision: https://reviews.llvm.org/D29808

llvm-svn: 296939
2017-03-04 01:23:30 +00:00
Daniel Berlin
210d3e0b90 NewGVN: Be consistent in what order we compare operands for swapping.
NFC.

llvm-svn: 296935
2017-03-04 00:44:43 +00:00
Eli Friedman
943f4f8da8 [MISched] Remove unused arguments. NFC.
llvm-svn: 296934
2017-03-04 00:42:55 +00:00
Sanjay Patel
5dae0360af [x86] check for commuted add pattern to find ADC/SBB
llvm-svn: 296933
2017-03-04 00:18:31 +00:00
Sanjay Patel
f1aa1056d9 [x86] add test to show failed recognition of commuted pattern; NFC
llvm-svn: 296931
2017-03-04 00:06:37 +00:00
Matthias Braun
8b8bd66a5d RegAllocGreedy: Follow-up to r296722
We can now end up in situations where we initiate LiveIntervalUnion
queries with different SubRanges against the same register unit, so the
assert() no longer holds in all cases. Just recalculate now when we know
the cache is out of date.

llvm-svn: 296928
2017-03-03 23:27:20 +00:00
Hans Wennborg
c1102a606f Revert r296865 "[ARM] fpscr read/write intrinsics not aware of each other"
It caused PR32134: "Cannot select: intrinsic %llvm.arm.get.fpscr".

llvm-svn: 296926
2017-03-03 23:19:31 +00:00
Tim Northover
e45d0b88df GlobalISel: constrain G_INSERT to inserting just one value per instruction.
It's much easier to reason about single-value inserts and no-one was actually
using the variadic variants before.

llvm-svn: 296923
2017-03-03 23:05:47 +00:00
Tim Northover
8e4a366014 GlobalISel: add merge/unmerge nodes for legalization.
These are simplified variants of the current G_SEQUENCE and G_EXTRACT, which
assume the individual parts will be contiguous, homogeneous, and occupy the
entirity of the larger register. This makes reasoning about them much easer
since you only have to look at the first register being merged and the result
to know what the instruction is doing.

I intend to gradually replace all uses of the more complicated sequence/extract
with these (or single-element insert/extracts), and then remove the older
variants. For now we start with legalization.

llvm-svn: 296921
2017-03-03 22:46:09 +00:00
Sanjay Patel
a104506995 [x86] refactor combineAddOrSubToADCOrSBB(); NFCI
The comments were wrong, and this is not an obvious transform.
This hopefully makes it clearer that we're missing the commuted
patterns for adds. It's less clear that this is actually a good
transform for all micro-arch.

This is prep work for trying to clean up the current adc/sbb 
codegen because it's definitely not happening optimally.

llvm-svn: 296918
2017-03-03 22:35:11 +00:00
Krzysztof Parzyszek
61a5cba5d0 Silence a warning, NFC
llvm-svn: 296917
2017-03-03 22:21:02 +00:00
Rong Xu
6e48b57f73 [PGO] Text format profile reader needs to clear the value profile
Summary:
Reset the ValueData for each function to avoid using the ones in
the previous function.

Reviewers: davidxl

Reviewed By: davidxl

Subscribers: llvm-commits, xur

Differential Revision: https://reviews.llvm.org/D30479

llvm-svn: 296916
2017-03-03 21:56:34 +00:00
Krzysztof Parzyszek
817f226056 Detect the existence of pthread_{s,g}etname_np in libpthread on Linux
Older Linux distributions may not have those functions.

llvm-svn: 296915
2017-03-03 21:53:12 +00:00
Zachary Turner
75b3d29cf1 Fix Threading path when LLVM_ENABLE_THREADS=0.
llvm-svn: 296914
2017-03-03 21:49:38 +00:00
Mehdi Amini
b0f9528da5 un-Xfail Fuzzer test that decided to pass on Green Dragon
It may be flacky, I'll turn it into unsupported if it fails again.

llvm-svn: 296913
2017-03-03 21:28:05 +00:00
Peter Collingbourne
86ef78c460 MC: De-duplicate the object streamer implementations of EmitFileDirective into MCObjectStreamer. NFCI.
llvm-svn: 296912
2017-03-03 21:22:06 +00:00
Chris Bieneman
9876c44779 [ObjectYAML] [DWARF] Abstract DWARF Initial Length values
In the DWARF 4 Spec section 7.2.2, data in many DWARF sections, and some DWARF structures start with "Initial Length Values", which are a 32-bit length, and an optional 64-bit length if the 32 bit value == UINT32_MAX.

This patch abstracts the Initial Length type in YAML, and extends its use to all the DWARF structures that are supported in the DWARFYAML code that have Initial Length values.

llvm-svn: 296911
2017-03-03 21:11:55 +00:00
Sanjay Patel
1ac5a5cbee [x86] regenerate checks; NFC
llvm-svn: 296908
2017-03-03 20:48:54 +00:00
Peter Collingbourne
baa45eb64c LTO: Hash the set of imported symbols for each module.
This set may affect code generation and is sensitive to link order (and
possibly in the future to the linker's choice of prevailing symbol), so we
need to include it.

Differential Revision: https://reviews.llvm.org/D30586

llvm-svn: 296907
2017-03-03 20:25:30 +00:00
Zachary Turner
56b7096cf5 [Windows] Remove the #include <eh.h> hack.
Prior to MSVC 2015 we had to manually include this header any
time we were going to include <thread> or <future> due to a
bug in MSVC's STL implementation.  This has been fixed in MSVC
for some time now, and we require VS 2015 minimum, so we can
remove this across all subprojects.

llvm-svn: 296906
2017-03-03 20:21:59 +00:00
Matthias Braun
66fc8808cd RegisterCoalescer: Simplify subrange splitting code; NFC
- Use slightly better variable names / compute in a more direct way.

llvm-svn: 296905
2017-03-03 19:05:34 +00:00
Zachary Turner
394896e64a Teach lit to expand glob expressions.
This will enable removing hacks throughout the codebase
in clang and compiler-rt that feed multiple inputs to a
testing utility by globbing, all of which are either disabled
on Windows currently or using xargs / find hacks.

Differential Revision: https://reviews.llvm.org/D30380

llvm-svn: 296904
2017-03-03 18:55:24 +00:00
Sanjoy Das
71ac933a38 Fix a compiler warning
llvm-svn: 296903
2017-03-03 18:53:09 +00:00
Zachary Turner
a7d6eb51b6 Add missing #includes for FreeBSD.
llvm-svn: 296902
2017-03-03 18:38:22 +00:00
Krzysztof Parzyszek
d151d23d21 Make TargetInstrInfo::isPredicable take a const reference, NFC
llvm-svn: 296901
2017-03-03 18:30:54 +00:00
Mike Aizatsky
df0432e5e2 [sancov] better input parameters validation
Differential Revision: https://reviews.llvm.org/D30370

llvm-svn: 296900
2017-03-03 18:22:20 +00:00
Zachary Turner
dd6a386236 Try again to appease the FreeBSD bot.
The actual logic was wrong, not just the type conversion.
This should get it correct.

llvm-svn: 296899
2017-03-03 18:21:04 +00:00
Sanjoy Das
9ecf4261b1 [LoopUnrolling] Peel loops with invariant backedge Phi input
Summary:
If a loop contains a Phi node which has an invariant input from back
edge, it is profitable to peel such loops (rather than unroll them) to
use the advantage that this Phi is always invariant starting from 2nd
iteration. After the 1st iteration is peeled, other optimizations can
potentially simplify calculations with this invariant.

Patch by Max Kazantsev!

Reviewers: sanjoy, apilipenko, igor-laevsky, anna, mkuper, reames

Reviewed By: mkuper

Subscribers: mkuper, mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D30161

llvm-svn: 296898
2017-03-03 18:19:15 +00:00
Sanjoy Das
f07ac23c21 [LoopUnrolling] Re-prioritize Peeling and Partial unrolling
Summary:
In current implementation the loop peeling happens after trip-count based partial unrolling and may
sometimes not happen at all due to it (for example, if trip count is known, but UP.Partial = false). This
is generally bad, the more than there are some situations where peeling is profitable even if the partial
unrolling is disabled.

This patch is a NFC which reorders peeling and partial unrolling application and prepares the code for
implementation of the said optimizations.

Patch by Max Kazantsev!

Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper

Reviewed By: mkuper

Subscribers: mkuper, llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D30243

llvm-svn: 296897
2017-03-03 18:19:10 +00:00
Sanjay Patel
1ba7dfb74b [x86] clean up materializeSBB(); NFCI
This is producing SBB where it is obviously not necessary, so it needs to be limited.

llvm-svn: 296894
2017-03-03 17:58:39 +00:00
Zachary Turner
9f4052c410 Try to appease the FreeBSD bots.
pthread_self() returns a pthread_t, but we were setting it to
an int.  It seems the cast to int when calling sysctl is still
the correct thing to do, though.

llvm-svn: 296892
2017-03-03 17:56:14 +00:00
Zachary Turner
251d51b2b8 Don't bring in llvm/Support/thread.h in Threading.cpp
Doing so defines the type llvm::thread.  On FreeBSD, we need
to call a macro which references its own ::thread type, which
causes an ambiguity due to ADL when inside of the llvm namespace.

Since we don't even need this unless LLVM_ENABLE_THREADS == 1,
we don't even need this type anyway, as it is always equal to
std::thread, so we can just use that directly.

llvm-svn: 296891
2017-03-03 17:39:24 +00:00
Zachary Turner
f98945c7a9 Add #include for unistd.h on Linux.
llvm-svn: 296890
2017-03-03 17:24:55 +00:00
Zachary Turner
471deac0c7 [Support] Provide access to current thread name/thread id.
Applications often need the current thread id when making
system calls, and some operating systems provide the notion
of a thread name, which can be useful in enabling better
diagnostics when debugging or logging.

This patch adds an accessor for the thread id, and "best effort"
getters and setters for the thread name.  Since this is
non critical functionality, no error is returned to indicate
that a platform doesn't support thread names.

Differential Revision: https://reviews.llvm.org/D30526

llvm-svn: 296887
2017-03-03 17:15:17 +00:00
Simon Pilgrim
f1e7abde01 Use APInt::setBits instead of OR'ing in a separate APInt::getBitsSet call
llvm-svn: 296886
2017-03-03 17:03:52 +00:00
Sanjay Patel
c4a1855ae2 [x86] regenerate checks; NFC
llvm-svn: 296883
2017-03-03 16:58:51 +00:00
Simon Pilgrim
a6820e165a Use APInt::getLowBitsSet instead of APInt::getBitsSet for lower bit mask creation
llvm-svn: 296882
2017-03-03 16:56:33 +00:00
Sanjay Patel
5d2d3733a5 [x86] regenerate checks; NFC
llvm-svn: 296881
2017-03-03 16:45:57 +00:00
Sanjay Patel
41ce531451 [x86] regenerate checks; NFC
llvm-svn: 296880
2017-03-03 16:42:43 +00:00
Simon Pilgrim
0055010fcf Use APInt::getOneBitSet instead of APInt::getBitsSet for sign bit mask creation
Avoids all the unnecessary extra bitrange creation/shift stages.

llvm-svn: 296879
2017-03-03 16:35:57 +00:00
Sanjay Patel
a5bf3341f1 [x86] regenerate checks; NFC
llvm-svn: 296877
2017-03-03 16:34:35 +00:00
Sanjay Patel
35b8b1e271 [x86] fix formatting; NFC
llvm-svn: 296875
2017-03-03 15:17:41 +00:00
Simon Pilgrim
a217d030ed Use APInt::getHighBitsSet instead of APInt::getBitsSet for upper bit mask creation
llvm-svn: 296874
2017-03-03 14:37:57 +00:00
Dmitry Preobrazhensky
38ef58d587 [AMDGPU][MC] Fix for Bug 30829 + LIT tests
Added code to check constant bus restrictions for VOP formats (only one SGPR value or literal-constant may be used by the instruction).
Note that the same checks are performed by SIInstrInfo::verifyInstruction (used by lowering code).
Added LIT tests.

llvm-svn: 296873
2017-03-03 14:31:06 +00:00
Benjamin Kramer
089fa87307 Revert "Re-apply "[GVNHoist] Move GVNHoist to function simplification part of pipeline.""
This reverts commit r296759. Miscompiles bash.

llvm-svn: 296872
2017-03-03 14:27:53 +00:00
Simon Pilgrim
f1692dc76e Use APInt::getOneBitSet instead of APInt::getBitsSet for sign bit mask creation
Avoids all the unnecessary extra bitrange creation/shift stages.

llvm-svn: 296871
2017-03-03 14:25:46 +00:00
Simon Pilgrim
044f8ed412 Fix Wdocumentation warning
llvm-svn: 296866
2017-03-03 12:09:11 +00:00
Ranjeet Singh
e9e99b10c8 [ARM] fpscr read/write intrinsics not aware of each other
The intrinsics __builtin_arm_get_fpscr and __builtin_arm_set_fpscr read and
write to the fpscr (Floating-Point Status and Control Register) register.

A bug exists in the __builtin_arm_get_fpscr intrinsic definition in llvm which
treats this intrinsic as a IntroNoMem which means it's not a memory access and
doesn't have any other side-effects. Having this property on this intrinsic
means that various optimizations can be done on this such as common
sub-expression elimination with other reads. This can cause issues if there has
been write to this register, e.g.

void foo(int *p) {
     p[0] = __builtin_arm_get_fpscr();
     __builtin_arm_set_fpscr(1);
     p[1] = __builtin_arm_get_fpscr();
}

in the above example the second read is currently CSE'd into the first read,
this is because llvm isn't aware that the write done by __builtin_arm_set_fpscr
effects the same register that __builtin_arm_get_fpscr reads from, to fix this
problem I've removed the property IntrNoMem so that __builtin_arm_get_fpscr is
treated as a memory access.

Differential Revision: https://reviews.llvm.org/D30542

llvm-svn: 296865
2017-03-03 11:40:07 +00:00
Mohammad Shahid
d8acf02cf1 [SLP] Fixes the bug due to absence of in order uses of scalars which needs to be available
for VectorizeTree() API.This API uses it for proper mask computation to be used in shufflevector IR.
The fix is to compute the mask for out of order memory accesses while building the vectorizable tree
instead of actual vectorization of vectorizable tree.It also needs to recompute the proper Lane for
external use of vectorizable scalars based on shuffle mask.

Reviewers: mkuper

Differential Revision: https://reviews.llvm.org/D30159

Change-Id: Ide8773ce0ad3562f3cf4d1a0ad0f487e2f60ce5d
llvm-svn: 296863
2017-03-03 10:02:47 +00:00
Chandler Carruth
7b066daf55 [SDAG] Revert r296476 (and r296486, r296668, r296690).
This patch causes compile times for some patterns to explode. I have
a (large, unreduced) test case that slows down by more than 20x and
several test cases slow down by 2x. I'm sending some of the test cases
directly to Nirav and following up with more details in the review log,
but this should unblock anyone else hitting this.

llvm-svn: 296862
2017-03-03 10:02:25 +00:00