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Commit Graph

208330 Commits

Author SHA1 Message Date
Georgii Rymar
f7c776770a [yaml2obj/obj2yaml] - Make Value/Size fields of Symbol optional.
When a field is optional we can use the `=<none>` syntax in macros.
This patch makes `Value`/`Size` fields of `Symbol` optional
and adds test cases for them.

Differential revision: https://reviews.llvm.org/D93010
2020-12-16 13:49:57 +03:00
Georgii Rymar
eb12cf3add [lib/Object] - Make ELFObjectFile::getSymbol() return Expected<>.
This was requested in comments for D93209:
https://reviews.llvm.org/D93209#inline-871192

D93209 fixes an issue with `ELFFile<ELFT>::getEntry`,
after what `getSymbol` starts calling `report_fatal_error` for previously
missed invalid cases.

This patch makes it return `Expected<>` and updates callers.
For few of them I had to add new `report_fatal_error` calls. But I see no
way to avoid it currently. The change would affects too many places, e.g:
`getSymbolBinding` and other methods are used from `ELFSymbolRef`
which is used in too many places across LLVM.

Differential revision: https://reviews.llvm.org/D93297
2020-12-16 13:14:23 +03:00
Georgii Rymar
e16531589c [llvm-readelf/obj] - Handle out-of-order PT_LOADs better.
This is https://bugs.llvm.org/show_bug.cgi?id=45698.

Specification says that
"Loadable segment entries in the program header table appear
in ascending order, sorted on the p_vaddr member."

Our `toMappedAddr()` relies on this condition. This patch
adds a warning when the sorting order of loadable segments is wrong.
In this case we force segments sorting and that allows
`toMappedAddr()` to work as expected.

Differential revision: https://reviews.llvm.org/D92641
2020-12-16 12:59:32 +03:00
Piotr Sobczak
1fb1c3cd05 [AMDGPU] Avoid calling copyFastMathFlags in wrong context
Calling Instruction::copyFastMathFlags() assumes the caller is
FPMathOperator. Avoid calling the function for instructions
that are not instances of FPMathOperator.
2020-12-16 10:22:51 +01:00
Sebastian Neubauer
20ade166d1 [AMDGPU] Allow no saddr for global addtid insts
I think the global_load/store_dword_addtid instructions support
switching off the scalar address.
Add assembler and disassembler support for this.

Differential Revision: https://reviews.llvm.org/D93288
2020-12-16 10:01:40 +01:00
Jan Svoboda
53d0b253a4 [clang][cli] Prevent double denormalization
If both flags created through BoolOption are CC1Option and the keypath has a non-default or non-implied value, the denormalizer gets called twice. If the denormalizer has the ability to generate both flags, we can end up generating the same flag twice.

Reviewed By: dexonsmith, Bigcheese

Differential Revision: https://reviews.llvm.org/D93094
2020-12-16 09:44:54 +01:00
Stanislav Mekhanoshin
8688622340 [AMDGPU] Print SCRATCH_EN field after the kernel
Differential Revision: https://reviews.llvm.org/D93353
2020-12-15 22:44:30 -08:00
Philip Reames
a55c1816ea [LV] Weaken a unnecessarily strong assert [NFC]
Account for the fact that (in the future) the latch might be a switch not a branch.  The existing code is correct, minus the assert.
2020-12-15 19:07:53 -08:00
Lang Hames
36c0911571 [JITLink][ORC] Enable creation / linking of raw jitlink::LinkGraphs.
Separates link graph creation from linking. This allows raw LinkGraphs to be
created and passed to a link. ObjectLinkingLayer is updated to support emission
of raw LinkGraphs in addition to object buffers.

Raw LinkGraphs can be created by in-memory compilers to bypass object encoding /
decoding (though this prevents caching, as LinkGraphs have do not have an
on-disk representation), and by utility code to add programatically generated
data structures to the JIT target process.
2020-12-16 14:01:50 +11:00
Zakk Chen
f62c427dbf [RISCV] Refine vector load/store tablegen pattern, NFC.
Refine tablegen pattern for vector load/store, and follow
D93012 to separate masked and unmasked definitions for
pseudo load/store instructions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93284
2020-12-15 18:55:55 -08:00
Philip Reames
babb17746f [LV] Extend dead instruction detection to multiple exiting blocks
Given we haven't yet enabled multiple exiting blocks, this is currently non functional, but it's an obvious extension which cleans up a later patch.

I don't think this is worth review (as it's pretty obvious), if anyone disagrees, feel feel to revert or comment and I will.
2020-12-15 18:46:32 -08:00
Krzysztof Parzyszek
377eef9f3b [Hexagon] Rename test case, NFC 2020-12-15 19:05:31 -06:00
Krzysztof Parzyszek
7bf57c181c [Hexagon] Temporarily disable vector realignment for non-HVX vectors 2020-12-15 19:03:07 -06:00
Krzysztof Parzyszek
a31ff2abea [Hexagon] Emit enough stores when aligning vector addresses 2020-12-15 18:59:53 -06:00
LLVM GN Syncbot
f211f158cb [gn build] Port b9c77542e23 2020-12-16 00:03:26 +00:00
Johannes Doerfert
05f471417e Revert "[OpenMP] Add initial support for omp [begin/end] assumes"
There is a build error with gcc-5 [0], investigating now.

[0] https://reviews.llvm.org/D91980#2456526

This reverts commit a5a14cbe7f87e01882ecaa14df5d596cbf38823a.
2020-12-15 18:03:10 -06:00
Reid Kleckner
45f3869c8b Document that AlignedCharArrayUnion exists to work around an MSVC bug
Differential Revision: https://reviews.llvm.org/D93355
2020-12-15 16:01:55 -08:00
Bangtian Liu
e77001771a Ensure SplitEdge to return the new block between the two given blocks
This PR implements the function splitBasicBlockBefore to address an
issue
that occurred during SplitEdge(BB, Succ, ...), inside splitBlockBefore.
The issue occurs in SplitEdge when the Succ has a single predecessor
and the edge between the BB and Succ is not critical. This produces
the result ‘BB->Succ->New’. The new function splitBasicBlockBefore
was added to splitBlockBefore to handle the issue and now produces
the correct result ‘BB->New->Succ’.

Below is an example of splitting the block bb1 at its first instruction.

/// Original IR
bb0:
	br bb1
bb1:
        %0 = mul i32 1, 2
	br bb2
bb2:
/// IR after splitEdge(bb0, bb1) using splitBasicBlock
bb0:
	br bb1
bb1:
	br bb1.split
bb1.split:
        %0 = mul i32 1, 2
	br bb2
bb2:
/// IR after splitEdge(bb0, bb1) using splitBasicBlockBefore
bb0:
	br bb1.split
bb1.split
	br bb1
bb1:
        %0 = mul i32 1, 2
	br bb2
bb2:

Differential Revision: https://reviews.llvm.org/D92200
2020-12-15 23:32:29 +00:00
Harald van Dijk
7019559b57 [X86] Add REX prefix for GOTTPOFF/TLSDESC relocs in x32 mode
The REX prefix is needed to allow linker relaxations: even if the
instruction we emit may not need it, the linker may change it to a
different instruction which does need it.
2020-12-15 23:07:34 +00:00
Fangrui Song
5dd827ba56 [IR] Delete deprecated DebugLoc::get 2020-12-15 14:53:12 -08:00
Johannes Doerfert
d6a9ea03f5 [OpenMP] Add initial support for omp [begin/end] assumes
The `assumes` directive is an OpenMP 5.1 feature that allows the user to
provide assumptions to the optimizer. Assumptions can refer to
directives (`absent` and `contains` clauses), expressions (`holds`
clause), or generic properties (`no_openmp_routines`, `ext_ABCD`, ...).

The `assumes` spelling is used for assumptions in the global scope while
`assume` is used for executable contexts with an associated structured
block.

This patch only implements the global spellings. While clauses with
arguments are "accepted" by the parser, they will simply be ignored for
now. The implementation lowers the assumptions directly to the
`AssumptionAttr`.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D91980
2020-12-15 16:51:34 -06:00
Johannes Doerfert
38aa2584d5 [OpenMP] Use assumptions during ICV tracking
The OpenMP 5.1 assumptions `no_openmp` and `no_openmp_routines` allow us
to ignore calls that would otherwise prevent ICV tracking.

Once we track more ICVs we might need to distinguish the ones that could
be impacted even with `no_openmp_routines`.

Reviewed By: sstefan1

Differential Revision: https://reviews.llvm.org/D92050
2020-12-15 16:51:34 -06:00
Johannes Doerfert
6230d2a2a4 [Clang][Attr] Introduce the assume function attribute
The `assume` attribute is a way to provide additional, arbitrary
information to the optimizer. For now, assumptions are restricted to
strings which will be accumulated for a function and emitted as comma
separated string function attribute. The key of the LLVM-IR function
attribute is `llvm.assume`. Similar to `llvm.assume` and
`__builtin_assume`, the `assume` attribute provides a user defined
assumption to the compiler.

A follow up patch will introduce an LLVM-core API to query the
assumptions attached to a function. We also expect to add more options,
e.g., expression arguments, to the `assume` attribute later on.

The `omp [begin] asssumes` pragma will leverage this attribute and
expose the functionality in the absence of OpenMP.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D91979
2020-12-15 16:51:34 -06:00
Johannes Doerfert
e4d8c28959 [OpenMPOpt][NFC] Clang format 2020-12-15 16:51:34 -06:00
Matt Arsenault
b5e8fa500a RegisterCoalescer: Remove phi-only subranges when erasing identity copies
Undef subranges are not present in the live range values, except when
they cross block boundaries. In this situation, a identity copy is
inside a loop, and one of the lanes is undefined. It only appears
alive inside the loop due to the copy. Once the copy was erased, it
would leave behind a segment inside the loop body with no
corresponding def anywhere in the program.

When RenameIndependentSubregs processed this dummy interval, it would
introduce a "Multiple connected components in live interval" verifier
error when IMPLICIT_DEFs were added to the other two blocks. I believe
there is a missing verifier check for this type of dummy interval.

I have found additional cases from the same fundamental problem in
other areas I haven't managed to fix yet (e.g. the commented out
prune_subrange_phi_value_* cases).
2020-12-15 17:36:32 -05:00
Hsiangkai Wang
e9597071e5 [RISCV] Define vfadd/vfsub/vfrsub intrinsics.
Define vfadd/vfsub/vfrsub intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93291
2020-12-16 06:31:47 +08:00
Hsiangkai Wang
0f1989f2f6 [RISCV] Define vmin/vminu/vmax/vmaxu intrinsics.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93218
2020-12-16 06:31:47 +08:00
Hsiangkai Wang
d53bf6755a [RISCV] Define vnsrl/vnsra intrinsics.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93207
2020-12-16 06:31:47 +08:00
Hsiangkai Wang
2ae9c17a2d [RISCV] Define vsll/vsrl/vsra intrinsics.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93193
2020-12-16 06:31:47 +08:00
Hsiangkai Wang
f62454ac21 [RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93175
2020-12-16 06:31:47 +08:00
Fangrui Song
0d6e89041d [docs][unittest][Go][StackProtector] Migrate deprecated DebugInfo::get to DILocation::get 2020-12-15 14:17:04 -08:00
Krzysztof Parzyszek
2c841246e5 [Hexagon] Fix bitcasting v1i8 -> i8 2020-12-15 16:01:24 -06:00
Matt Arsenault
31e0b0c671 GlobalISel: Fix generic handling of single outgoing call arguments
Simply call the argument handler like is done for the incoming
case. This will allow removal of hacks in the AMDGPU call lowering in
a future change.
2020-12-15 17:00:27 -05:00
Matt Arsenault
ddc572a7c2 AMDGPU: Remove redundant CCAction for i1 2020-12-15 17:00:27 -05:00
Craig Topper
de79bbfab5 [RISCV] Only custom legalize i32 arguments to vector intrinsics on RV64. 2020-12-15 13:54:41 -08:00
Roman Lebedev
f45051c79a [NFCI][SimplifyCFG] Add basic scaffolding for gradually making the pass DomTree-aware
Two observations:
1. Unavailability of DomTree makes it impossible to make
  `FoldBranchToCommonDest()` transform in certain cases,
   where the successor is dominated by predecessor,
   because we then don't have PHI's, and can't recreate them,
   well, without handrolling 'is dominated by' check,
   which doesn't really look like a great solution to me.
2. Avoiding invalidating DomTree in SimplifyCFG will
   decrease the number of `Dominator Tree Construction` by 5
   (from 28 now, i.e. -18%) in `-O3` old-pm pipeline
   (as per `llvm/test/Other/opt-O3-pipeline.ll`)
   This might or might not be beneficial for compile time.

So the plan is to make SimplifyCFG preserve DomTree, and then
eventually make DomTree fully required and preserved by the pass.

Now, SimplifyCFG is ~7KLOC. I don't think it will be nice
to do all this uplifting in a single mega-commit,
nor would it be possible to review it in any meaningful way.

But, i believe, it should be possible to do this in smaller steps,
introducing the new behavior, in an optional way, off-by-default,
opt-in option, and gradually fixing transforms one-by-one
and adding the flag to appropriate test coverage.

Then, eventually, the default should be flipped,
and eventually^2 the flag removed.

And that is what is happening here - when the new off-by-default option
is specified, DomTree is required and is claimed to be preserved,
and SimplifyCFG-internal assertions verify that the DomTree is still OK.
2020-12-16 00:38:00 +03:00
Roman Lebedev
bd5d92efea [NFC][Tests][SimplifyCFG] Trim whitespaces at the end of lines 2020-12-16 00:38:00 +03:00
Baptiste Saleil
8860fc8cf0 [PowerPC] Enable paired vector type and intrinsics when MMA is disabled
This patch enables the Clang type __vector_pair and its associated LLVM
intrinsics even when MMA is disabled. With this patch, the type is now controlled
by the PPC paired-vector-memops option. The builtins and intrinsics will be
renamed to drop the mma prefix in another patch.

Differential Revision: https://reviews.llvm.org/D91819
2020-12-15 15:14:11 -06:00
Philip Reames
845bb03637 [LV] Restructure handling of -prefer-predicate-over-epilogue option [NFC]
This should be purely non-functional.  When touching this code for another reason, I found the handling of the PredicateOrDontVectorize piece here very confusing.  Let's make it an explicit state (instead of an implicit combination of two variables), and use early return for options/hint processing.
2020-12-15 12:38:13 -08:00
Tony
2b79dcd0a2 [AMDGPU] Clarify scratch initialization
- Clarify documentation on initializing scratch.
- Rename compute_pgm_rsrc2 field for enabling scratch from
  ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET to
  ENABLE_PRIVATE_SEGMENT to match hardware definition.

Differential Revision: https://reviews.llvm.org/D93271
2020-12-15 20:14:20 +00:00
Philip Reames
3c15ecb483 [tests] fix an accidental target dependence added in 99ac8868 2020-12-15 11:07:30 -08:00
Philip Reames
b2e50ca8e1 [tests][LV] precommit tests for D93317 2020-12-15 10:53:34 -08:00
Mircea Trofin
3b45486589 [NFC] update extract-lowbits.ll and scalar-pf-to-i64.ll
Auto-updated with update_llc_test_checks
2020-12-15 10:04:45 -08:00
Kevin P. Neal
dcfb05f50c Revert "[FPEnv] Teach the IRBuilder about invoke's correct use of the strictfp attribute."
The test is busted on some hosts that aren't the one I'm using.

This reverts commit 67a1ffd88ac08526bb6cfc7b3f607e6668ba1c70.
2020-12-15 12:58:47 -05:00
Mircea Trofin
23e08603e3 [NFC] Update extract-bits.ll
Running update_llc_test_checks adds @PLT annotations to a number of
calls.
2020-12-15 09:52:17 -08:00
Kevin P. Neal
c61aa5bf2a [FPEnv] Teach the IRBuilder about invoke's correct use of the strictfp attribute.
Similar to D69312, and documented in D69839, the IRBuilder needs to add
the strictfp attribute to invoke instructions when constrained floating
point is enabled.

Differential Revision: https://reviews.llvm.org/D93134
2020-12-15 12:38:10 -05:00
Simon Pilgrim
e270201f09 [X86] Regenerate avxvnni.ll tests - remove unused prefix. NFCI. 2020-12-15 17:35:32 +00:00
Simon Pilgrim
1fa0a52f0b [X86] Explicitly use SDValue instead of auto. NFCI.
Fix static analyzer warning about not using a SDValue&
2020-12-15 17:27:25 +00:00
Simon Pilgrim
76b4fd1b08 SeparateConstOffsetFromGEP::lowerToSingleIndexGEPs - don't use dyn_cast_or_null. NFCI.
ResultPtr is guaranteed to be non-null - and using dyn_cast_or_null causes unnecessary static analyzer warnings.

We can't say the same for FirstResult AFAICT, so keep dyn_cast_or_null for that.
2020-12-15 17:27:25 +00:00
Amy Huang
eedfec2ca8 [llvm-symbolizer] Add missing include for config.h
The cmake variable LLVM_ENABLE_DIA_SDK was being used here but
was undefined because config.h wasn't included.

Differential Revision: https://reviews.llvm.org/D93309
2020-12-15 09:20:31 -08:00