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Commit Graph

265 Commits

Author SHA1 Message Date
Jim Laskey
f9f462bc5e Now that the ISel is available, it's possible to create a default instruction
scheduler creator.

llvm-svn: 29452
2006-08-01 19:14:14 +00:00
Jim Laskey
f5e160063e 1. Change use of "Cache" to "Default".
2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.

More to follow.

llvm-svn: 29450
2006-08-01 18:29:48 +00:00
Jim Laskey
b92b14f422 Introducing plugable register allocators and instruction schedulers.
llvm-svn: 29434
2006-08-01 14:21:23 +00:00
Evan Cheng
c1483b5e72 PIC jump table entries are always 32-bit even in 64-bit mode.
llvm-svn: 29422
2006-08-01 01:03:13 +00:00
Nate Begeman
952d922bf1 Code cleanups, per review
llvm-svn: 29347
2006-07-27 16:46:58 +00:00
Nate Begeman
3d5f5b4e8b Support jump tables when in PIC relocation model
llvm-svn: 29318
2006-07-27 01:13:04 +00:00
Chris Lattner
77e6cda5d0 Mems can be in the output list also. This is the second half of a fix for
PR833

llvm-svn: 29224
2006-07-20 19:02:21 +00:00
Chris Lattner
496bd3fbf6 Use hidden visibility to make symbols in an anonymous namespace get
dropped.  This shrinks libllvmgcc.dylib another 67K

llvm-svn: 28975
2006-06-28 23:17:24 +00:00
Evan Cheng
c4d878dc56 Consistency. EXTRACT_ELEMENT index operand should have ptr type.
llvm-svn: 28795
2006-06-15 08:11:54 +00:00
Chris Lattner
2d4ba3f9ca Make sure to update the CFG correctly if a switch only has a default dest.
This fixes CodeGen/Generic/2006-06-12-LowerSwitchCrash.ll

llvm-svn: 28755
2006-06-12 18:25:29 +00:00
Chris Lattner
a05c244289 Fix X86/inline-asm.ll:test2, a case where an input value was implicitly
truncated.

llvm-svn: 28733
2006-06-08 18:27:11 +00:00
Chris Lattner
963fd11359 Fix Regression/CodeGen/X86/inline-asm.ll, a case where inline asm causes
implement extension of a register.

llvm-svn: 28731
2006-06-08 18:22:48 +00:00
Evan Cheng
58bfb4e600 Make CALL node consistent with RET node. Signness of value has type MVT::i32
instead of MVT::i1. Either is fine except MVT::i32 is probably a legal type
for most (if not all) platforms while MVT::i1 is not.

llvm-svn: 28511
2006-05-26 23:13:20 +00:00
Evan Cheng
f53c4cc192 Change RET node to include signness information of the return values. e.g.
RET chain, value1, sign1, value2, sign2

llvm-svn: 28509
2006-05-26 23:09:09 +00:00
Evan Cheng
920d9c86f1 CALL node change: now including signness of every argument.
llvm-svn: 28461
2006-05-25 00:55:32 +00:00
Evan Cheng
6909147763 -enable-unsafe-fp-math implies -enable-finite-only-fp-math
llvm-svn: 28437
2006-05-23 18:18:46 +00:00
Vladimir Prus
125917432a Fix missing include
llvm-svn: 28435
2006-05-23 13:43:15 +00:00
Evan Cheng
19e9e63dcd Incorrect SETCC CondCode used for FP comparisons.
llvm-svn: 28433
2006-05-23 06:40:47 +00:00
Chris Lattner
b2ecc1b1e7 Fix the result of the call to use a correct vbitconvert. There is no need to
use getPackedTypeBreakdown at all here.

llvm-svn: 28365
2006-05-17 20:49:36 +00:00
Chris Lattner
924f3fed13 Correct a previous patch which broke CodeGen/PowerPC/vec_call.ll
llvm-svn: 28364
2006-05-17 20:43:21 +00:00
Evan Cheng
00f391f87b Fixed a LowerCallTo and LowerArguments bug. They were introducing illegal
VBIT_VECTOR nodes. There were some confusion about the semantics of
getPackedTypeBreakdown(). e.g. for <4 x f32> it returns 1 and v4f32, not 4,
and f32.

llvm-svn: 28352
2006-05-17 18:16:39 +00:00
Chris Lattner
30f61c8bb1 Add support for calls that pass and return legal vectors.
llvm-svn: 28340
2006-05-16 23:39:44 +00:00
Chris Lattner
01f4f28837 Add a new ISD::CALL node, make the default impl of TargetLowering::LowerCallTo
produce it.

llvm-svn: 28338
2006-05-16 22:53:20 +00:00
Chris Lattner
ba1dfc1da7 Add a chain to FORMAL_ARGUMENTS. This is a minimal port of the X86 backend,
it doesn't currently use/maintain the chain properly.  Also, make the
X86ISelLowering.cpp file 80-col clean.

llvm-svn: 28320
2006-05-16 06:45:34 +00:00
Chris Lattner
fdd62b9073 Move function-live-in-handling code from the sdisel code to the scheduler.
This code should be emitted after legalize, so it can't be in sdisel.

Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG.  The X86 backend is the only one currently using this hook.

llvm-svn: 28315
2006-05-16 06:10:58 +00:00
Evan Cheng
7bb257e178 Revert an un-intended change
llvm-svn: 28278
2006-05-13 05:53:47 +00:00
Chris Lattner
9e29384a4b Remove dead vars
llvm-svn: 28255
2006-05-12 18:06:45 +00:00
Evan Cheng
cb2a0f392c Refactor scheduler code. Move register-reduction list scheduler to a
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.

llvm-svn: 28226
2006-05-11 23:55:42 +00:00
Nate Begeman
1f359b07de Make emission of jump tables a bit less conservative; they are now required
to be only 31.25% dense, rather than 75% dense.

llvm-svn: 28165
2006-05-08 16:51:36 +00:00
Chris Lattner
02d3258820 When inserting casts, be careful of where we put them. We cannot insert
a cast immediately before a PHI node.

This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll

llvm-svn: 28143
2006-05-06 09:10:37 +00:00
Chris Lattner
229d3e3c2d More aggressively sink GEP offsets into loops. For example, before we
generated:

        movl 8(%esp), %eax
        movl %eax, %edx
        addl $4316, %edx
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, (%edx)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
        movl %edx, 4460(%eax)
        ret
...

Now we generate:

        movl 8(%esp), %eax
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, 4316(%eax)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
        movl %ecx, 4460(%eax)
        ret

... which uses one fewer register.

llvm-svn: 28129
2006-05-05 21:17:49 +00:00
Chris Lattner
56694d0bb0 Sink noop copies into the basic block that uses them. This reduces the number
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.

This reduces the load on the coallescer and register allocator.  For example
on a codec on X86, we went from:

   1643 asm-printer           - Number of machine instrs printed
    419 liveintervals         - Number of loads/stores folded into instructions
   1144 liveintervals         - Number of identity moves eliminated after coalescing
   1022 liveintervals         - Number of interval joins performed
    282 liveintervals         - Number of intervals after coalescing
   1304 liveintervals         - Number of original intervals
     86 regalloc              - Number of times we had to backtrack
1.90232 regalloc              - Ratio of intervals processed over total intervals
     40 spiller               - Number of values reused
    182 spiller               - Number of loads added
    121 spiller               - Number of stores added
    132 spiller               - Number of register spills
      6 twoaddressinstruction - Number of instructions commuted to coalesce
    360 twoaddressinstruction - Number of two-address instructions

to:

   1636 asm-printer           - Number of machine instrs printed
    403 liveintervals         - Number of loads/stores folded into instructions
   1155 liveintervals         - Number of identity moves eliminated after coalescing
   1033 liveintervals         - Number of interval joins performed
    279 liveintervals         - Number of intervals after coalescing
   1312 liveintervals         - Number of original intervals
     76 regalloc              - Number of times we had to backtrack
1.88998 regalloc              - Ratio of intervals processed over total intervals
      1 spiller               - Number of copies elided
     41 spiller               - Number of values reused
    191 spiller               - Number of loads added
    114 spiller               - Number of stores added
    128 spiller               - Number of register spills
      4 twoaddressinstruction - Number of instructions commuted to coalesce
    356 twoaddressinstruction - Number of two-address instructions

On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted.  It increases the number
of register coallesces.

llvm-svn: 28115
2006-05-05 01:04:50 +00:00
Nate Begeman
95a4f191e0 Finish up the initial jump table implementation by allowing jump tables to
not be 100% dense.  Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.

llvm-svn: 28079
2006-05-03 03:48:02 +00:00
Owen Anderson
71bc529dfa Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
This fixes PR 759.

llvm-svn: 28074
2006-05-03 01:29:57 +00:00
Evan Cheng
9f21c2daf4 Remove the temporary option: -no-isel-fold-inflight
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
Evan Cheng
f843942504 TargetLowering::LowerArguments should return a VBIT_CONVERT of
FORMAL_ARGUMENTS SDOperand in the return result vector.

llvm-svn: 28009
2006-04-28 05:25:15 +00:00
Evan Cheng
ff5a88b62e Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
node can be folded.

llvm-svn: 28003
2006-04-28 02:09:19 +00:00
Evan Cheng
a6081bc674 Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
(VAND, VADD, etc.). Legalizer will assert otherwise.

llvm-svn: 27991
2006-04-27 08:29:42 +00:00
Evan Cheng
b54140b0d6 Don't forget return void.
llvm-svn: 27974
2006-04-25 23:03:35 +00:00
Nate Begeman
7bb910dbe7 Fix the updating of the machine CFG when a PHI node was in a successor of
the jump table's range check block.  This re-enables 100% dense jump tables
by default on PPC & x86

llvm-svn: 27952
2006-04-23 06:26:20 +00:00
Nate Begeman
6cfb33a42c Turn of jump tables for a bit, there are still some issues to work out with
updating the machine CFG.

llvm-svn: 27949
2006-04-22 23:51:56 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Chris Lattner
8f7c394f3a The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
miscompares).  Switch RISC targets to use the list-td scheduler, which isn't.

llvm-svn: 27933
2006-04-21 17:16:16 +00:00
Chris Lattner
70d68fcfcb Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
llvm-svn: 27604
2006-04-12 16:20:43 +00:00
Chris Lattner
2c57f7285e Add code generator support for VSELECT
llvm-svn: 27542
2006-04-08 22:22:57 +00:00
Chris Lattner
fc546e1780 Codegen shufflevector as VVECTOR_SHUFFLE
llvm-svn: 27529
2006-04-08 04:15:24 +00:00
Chris Lattner
234481e1ba Stub out shufflevector
llvm-svn: 27514
2006-04-08 01:19:25 +00:00
Chris Lattner
fe2926cf46 Make a vector live across blocks have the correct Vec type. This fixes
CodeGen/X86/2006-04-04-CrossBlockCrash.ll

llvm-svn: 27436
2006-04-05 06:54:42 +00:00
Chris Lattner
389e309bfb Intrinsics that just load from memory can be treated like loads: they don't
have to serialize against each other.  This allows us to schedule lvx's
across each other, for example.

llvm-svn: 27346
2006-04-02 03:41:14 +00:00
Chris Lattner
badebf1c9b Add a new -view-legalize-dags command line option
llvm-svn: 27342
2006-04-02 03:07:27 +00:00