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f8905e9718
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12242 Commits

Author SHA1 Message Date
Ted Kremenek
f8905e9718 Update CMake file. 
llvm-svn: 86325
 2009-11-07 03:26:59 +00:00
Kenneth Uildriks
91ceaa85a2 Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers 
llvm-svn: 86324
 2009-11-07 02:11:54 +00:00
Johnny Chen
5158450544 My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm 
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0).  The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.

llvm-svn: 86319
 2009-11-07 00:54:36 +00:00
Jim Grosbach
71c5411651 80-columns 
llvm-svn: 86310
 2009-11-07 00:13:30 +00:00
Evan Cheng
6e3e66375a - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
 2009-11-06 23:52:48 +00:00
Anton Korobeynikov
dca40933ee Honour subreg machine operands during asmprinting 
llvm-svn: 86303
 2009-11-06 23:45:15 +00:00
Bob Wilson
e79354a831 Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301
 2009-11-06 23:33:28 +00:00
Evan Cheng
aaf30ce699 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
llvm-svn: 86294
 2009-11-06 22:24:13 +00:00
Daniel Dunbar
4daaf9d3f4 Pass StringRef by value. 
llvm-svn: 86251
 2009-11-06 10:58:06 +00:00
Dan Gohman
ada358e6a2 Factor out the printing of the leading tab into printInlineAsm. 
llvm-svn: 86199
 2009-11-06 00:04:54 +00:00
Dan Gohman
1a8616a0d7 Use SUBREG_TO_REG instead of INSERT_SUBREG to model x86-64's 
implicit zero-extend.

llvm-svn: 86196
 2009-11-05 23:53:08 +00:00
Dan Gohman
eec0f1c506 Remove uninteresting and confusing debug output. 
llvm-svn: 86149
 2009-11-05 18:47:09 +00:00
Chris Lattner
7f61fbfcca add a note from PR5313 
llvm-svn: 86146
 2009-11-05 18:19:19 +00:00
Mon P Wang
0669a8df22 Reintroduce support for overloading target intrinsics 
llvm-svn: 86114
 2009-11-05 03:19:08 +00:00
Jim Grosbach
ef37391033 Grammar. 
llvm-svn: 86068
 2009-11-04 23:20:40 +00:00
Jim Grosbach
2867641b64 Now that the memory leak from McCat/08-main has been fixed (86056), re-enable 
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.

llvm-svn: 86064
 2009-11-04 23:11:07 +00:00
Jim Grosbach
c0cabc9119 If a function has no stack frame at all, dynamic realignment isn't necessary. 
llvm-svn: 86057
 2009-11-04 22:41:51 +00:00
Jim Grosbach
c8a01556f4 dynamic stack realignment necessitates scanning the floating point callee- 
saved instructions even if no stack adjustment for those saves is needed.

llvm-svn: 86056
 2009-11-04 22:41:00 +00:00
Bob Wilson
25738f9e79 Add PowerPC codegen for indirect branches. 
llvm-svn: 86050
 2009-11-04 21:31:18 +00:00
Jakob Stoklund Olesen
f775e222e0 Print out an informative comment for KILL instructions. 
The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.

With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.

llvm-svn: 86041
 2009-11-04 19:24:37 +00:00
Evan Cheng
22121f4c69 The .n suffix must go after the predicate. 
llvm-svn: 86019
 2009-11-04 07:38:48 +00:00
Evan Cheng
1a06b12330 Use ldr.n to workaround a darwin assembler bug. 
llvm-svn: 85980
 2009-11-04 00:00:39 +00:00
Evan Cheng
b50510c510 Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long. 
llvm-svn: 85965
 2009-11-03 23:13:34 +00:00
Evan Cheng
caab17007b fconsts / fconstd immediate should be proceeded with #. 
llvm-svn: 85952
 2009-11-03 21:59:33 +00:00
Anton Korobeynikov
de7cbab064 Move subtarget check upper for NEON reg-reg fixup pass. 
llvm-svn: 85914
 2009-11-03 18:46:11 +00:00
Evan Cheng
1d4575274c Trim unnecessary include. 
llvm-svn: 85878
 2009-11-03 07:08:08 +00:00
Bob Wilson
97331f70ca For Thumb indirect branches, use "mov pc, reg" which does not switch 
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874
 2009-11-03 06:29:56 +00:00
Evan Cheng
ed22395c61 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Evan Cheng
2807af42c0 Clean up copyRegToReg. 
llvm-svn: 85870
 2009-11-03 05:51:39 +00:00
Evan Cheng
9bedf1b587 Add QPR_8 as a superreg class of SPR_8 and DPR_8. 
llvm-svn: 85869
 2009-11-03 05:50:57 +00:00
Ted Kremenek
a474928cda Update CMake file. 
llvm-svn: 85861
 2009-11-03 04:14:12 +00:00
Anton Korobeynikov
ff29071cc6 Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time. 
llvm-svn: 85850
 2009-11-03 01:04:26 +00:00
Anton Korobeynikov
48b30c79be Revert r85049, it is causing PR5367 
llvm-svn: 85847
 2009-11-03 00:24:48 +00:00
Bob Wilson
7e071e14eb Revert previous change to a comment. The BlockAddresses go in the 
constant pool so they don't get wrapped separately.

llvm-svn: 85844
 2009-11-03 00:02:05 +00:00
Bob Wilson
3144715b53 Put BlockAddresses into ARM constant pools. 
llvm-svn: 85824
 2009-11-02 20:59:23 +00:00
Kevin Enderby
633b294095 Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should 
have been passed as a reference.

llvm-svn: 85823
 2009-11-02 20:14:39 +00:00
David Goodwin
9aa890eab6 Fix schedule model for BFC. 
llvm-svn: 85809
 2009-11-02 17:28:36 +00:00
Bob Wilson
0c213bed8b Hyphenate some comments. 
llvm-svn: 85808
 2009-11-02 17:10:37 +00:00
Bob Wilson
6eb4f53d90 Add support for BlockAddress values in ARM constant pools. 
llvm-svn: 85806
 2009-11-02 16:59:06 +00:00
Bob Wilson
ac53e0c640 Prune unnecessary include. 
llvm-svn: 85805
 2009-11-02 16:58:31 +00:00
Evan Cheng
e79ff8a615 These are done / no longer care. 
llvm-svn: 85798
 2009-11-02 07:58:25 +00:00
Evan Cheng
532dfd431f Add an entry. 
llvm-svn: 85797
 2009-11-02 07:51:19 +00:00
Evan Cheng
57f7c7c914 Unbreak ARMBaseRegisterInfo::copyRegToReg. 
llvm-svn: 85787
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov
09147da530 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
llvm-svn: 85767
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov
9737bfedeb Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
 2009-11-02 00:11:39 +00:00
Anton Korobeynikov
ed410a8ee3 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Anton Korobeynikov
3ba3789153 Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) 
llvm-svn: 85764
 2009-11-02 00:10:38 +00:00
Evan Cheng
a409c074c8 Fix a couple more places where we are creating ld / st instructions without memoperands. 
llvm-svn: 85746
 2009-11-01 22:04:35 +00:00
Evan Cheng
4a0d47f209 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
llvm-svn: 85743
 2009-11-01 21:12:51 +00:00
Chris Lattner
4cf2980e59 improve x86 codegen support for blockaddress. We now compile 
the testcase into:

_test1:                                                     ## @test1
## BB#0:                                                    ## %entry
	leaq	L_test1_bb6(%rip), %rax
	jmpq	*%rax
L_test1_bb:                                                 ## Address Taken
LBB1_1:                                                     ## %bb
	movb	$1, %al
	ret
L_test1_bb6:                                                ## Address Taken
LBB1_2:                                                     ## %bb6
	movb	$2, %al
	ret

Note, it is very very strange that BlockAddressSDNode doesn't carry 
around TargetFlags.  Dan, please fix this.

llvm-svn: 85703
 2009-11-01 03:25:03 +00:00