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Commit Graph

40976 Commits

Author SHA1 Message Date
Evan Cheng
f993be4cc8 If TargetSelectInstruction returns true, move to next instruction.
llvm-svn: 55692
2008-09-03 06:43:41 +00:00
Evan Cheng
0c40be80aa Make UpdateValueMap, createResultReg, etc. protected instead of private so they can used by target hooks.
llvm-svn: 55691
2008-09-03 06:43:10 +00:00
Nick Lewycky
3b35dcc455 Don't apply this transform to vectors. Fixes PR2756.
llvm-svn: 55690
2008-09-03 06:24:21 +00:00
Nick Lewycky
57cebeaeba Don't crash when trying to constant fold a vector with some elements that can't
be folded. Instead, fail to fold the entire vector.

We could also return a vector with some elements folded and some not. If anyone
thinks that's a better approach, please speak up!

llvm-svn: 55689
2008-09-03 05:54:33 +00:00
Ted Kremenek
b7236d215b Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems.
llvm-svn: 55687
2008-09-03 02:54:11 +00:00
Evan Cheng
4cef3f6ce1 Unbreak fast isel.
llvm-svn: 55685
2008-09-03 01:04:47 +00:00
Devang Patel
5fa8cc79ed Add additional check to ensure that iv is canonicalized.
llvm-svn: 55682
2008-09-03 00:29:13 +00:00
Devang Patel
4dfecae8fe Check iteration count.
llvm-svn: 55680
2008-09-03 00:10:56 +00:00
Evan Cheng
43c7084625 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
llvm-svn: 55679
2008-09-03 00:03:49 +00:00
Devang Patel
df5dce4aa8 While removing PHI, use basicblock to identify incoming value.
llvm-svn: 55678
2008-09-03 00:02:42 +00:00
Devang Patel
5659d2508e s/FP_AlwaysInline/FN_NOTE_AlwaysInline/g
llvm-svn: 55676
2008-09-02 22:43:57 +00:00
Devang Patel
a1e2066b1d If all IV uses are extending integer IV then change the type of IV itself, if possible.
llvm-svn: 55674
2008-09-02 22:18:08 +00:00
Devang Patel
cda9086d29 respect inline=never and inline=always notes.
llvm-svn: 55673
2008-09-02 22:16:13 +00:00
Evan Cheng
5e0e6dfc7f 80 col violations.
llvm-svn: 55668
2008-09-02 21:59:13 +00:00
Devang Patel
631122c84b Read and write function notes.
llvm-svn: 55657
2008-09-02 21:47:13 +00:00
Devang Patel
d131eb6bfb Use bitwise AND.
llvm-svn: 55656
2008-09-02 21:46:44 +00:00
Dale Johannesen
1962ef8546 New testcase for targets without 64-bit atomics;
xfail old test for ppc.

llvm-svn: 55651
2008-09-02 21:19:30 +00:00
Devang Patel
468829b883 Function notes tests.
llvm-svn: 55648
2008-09-02 20:58:16 +00:00
Devang Patel
4b52a398c3 Print function notes.
llvm-svn: 55647
2008-09-02 20:56:33 +00:00
Devang Patel
f06ad159e9 Parse function notes.
llvm-svn: 55646
2008-09-02 20:52:40 +00:00
Devang Patel
863655cd40 Initialize function notes.
llvm-svn: 55645
2008-09-02 20:51:15 +00:00
Dale Johannesen
46f19abcec Fix some bugs in the code sequences for atomics.
llvm-svn: 55643
2008-09-02 20:30:23 +00:00
Dan Gohman
9969b223c7 Ensure that HandlePHINodesInSuccessorBlocks is run for all blocks,
even in FastISel mode in the case where FastISel successfully 
selects all the instructions. 

llvm-svn: 55641
2008-09-02 20:17:56 +00:00
Devang Patel
badf2b9315 Getter and setter for function notes.
llvm-svn: 55638
2008-09-02 18:33:55 +00:00
Daniel Dunbar
4929090fb1 Reapply majority of r55557 but with the changes to compilation flags
disabled until issues with gcc 4.1 on linux 32-bit are resolved.

llvm-svn: 55636
2008-09-02 17:35:16 +00:00
Nuno Lopes
8d481ade2f plug memleak: destroy internal buffer
llvm-svn: 55632
2008-09-02 12:06:08 +00:00
Nuno Lopes
5c40eb8e05 plug a little memleak in verifyFunction()
# first commit to llvm, so whatch out :)

llvm-svn: 55631
2008-09-02 11:30:10 +00:00
Matthijs Kooijman
96700eceda Revert r55557, it is causing linking failures on 32bit linux.
llvm-svn: 55628
2008-09-02 09:51:00 +00:00
Evan Cheng
15fd1af657 MMI may be null.
llvm-svn: 55626
2008-09-02 08:14:01 +00:00
Evan Cheng
126bd60288 Add Mac OS X compatible JIT callback routine.
llvm-svn: 55625
2008-09-02 07:49:03 +00:00
Evan Cheng
e97c48a34a Revamp ARM JIT.
llvm-svn: 55624
2008-09-02 06:52:38 +00:00
Evan Cheng
9817be2f96 Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
llvm-svn: 55623
2008-09-02 06:51:36 +00:00
Gabor Greif
632fa3a318 Provide two overloads of AnalyzeNewNode.
The first can update the SDNode in an SDValue
while the second is called with SDNode* and
returns a possibly updated SDNode*.

This patch has no intended functional impact,
but helps eliminating ugly temporary SDValues.

llvm-svn: 55608
2008-09-01 15:10:19 +00:00
Duncan Sands
efc82024e0 Even though no caller actually uses the new value
(what matters is that it is added to the worklist),
it seems more logical to return it.

llvm-svn: 55606
2008-09-01 13:11:13 +00:00
Duncan Sands
044fcaf6b4 Turn this legalize types test on.
llvm-svn: 55605
2008-09-01 12:00:55 +00:00
Duncan Sands
0338e9f60d Add a small pass that sets the readnone/readonly
attributes on functions, based on the result of
alias analysis.  It's not hardwired to use
GlobalsModRef even though this is the only (AFAIK)
alias analysis that results in this pass actually
doing something.  Enable as follows:
  opt ... -globalsmodref-aa -markmodref ...
Advantages of this pass: (1) records the result
of globalsmodref in the bitcode, meaning it is
available for use by later passes (currently
the pass manager isn't smart enough to magically
make an advanced alias analysis available to all
later passes), which may expose more optimization
opportunities; (2) hopefully speeds up compilation
when code is optimized twice, for example when a
file is compiled to bitcode, then later LTO is done
on it: marking functions readonly/readnone when
producing the initial bitcode should speed up alias
analysis during LTO; (3) good for discovering that
globalsmodref doesn't work very well :)
Not currently turned on by default.

llvm-svn: 55604
2008-09-01 11:40:11 +00:00
Evan Cheng
738426a2a1 Control flow instruction encodings.
llvm-svn: 55601
2008-09-01 08:25:56 +00:00
Evan Cheng
36170e63a3 ldm / stm instruction encodings.
llvm-svn: 55599
2008-09-01 07:48:18 +00:00
Evan Cheng
01019d7909 AXI2 and AXI3 instruction encodings.
llvm-svn: 55598
2008-09-01 07:34:13 +00:00
Evan Cheng
fdae49e627 Reorganize instruction formats again; AXI1 encoding.
llvm-svn: 55597
2008-09-01 07:19:00 +00:00
Evan Cheng
26305b192f addrmode3 instruction encodings.
llvm-svn: 55596
2008-09-01 07:00:14 +00:00
Evan Cheng
eb40cb3e42 Reorganize some instruction format definitions. No functionality change.
llvm-svn: 55594
2008-09-01 01:51:14 +00:00
Evan Cheng
fa095aec1e Rest of addrmode2 instruction encodings.
llvm-svn: 55593
2008-09-01 01:27:33 +00:00
Evan Cheng
4c8338c0d3 Addr2 word / byte load encodings.
llvm-svn: 55591
2008-08-31 19:02:21 +00:00
Evan Cheng
94f3d276c6 Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
llvm-svn: 55590
2008-08-31 18:32:16 +00:00
Gabor Greif
7db742d8c2 fix a bunch of 80-col violations
llvm-svn: 55588
2008-08-31 15:37:04 +00:00
Bill Wendling
297eb080b6 Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.

llvm-svn: 55582
2008-08-31 02:59:23 +00:00
Bill Wendling
8faa2f3ec4 Expand for ROTR with MVT::i64.
Dale, Could you please review this?

llvm-svn: 55581
2008-08-31 02:53:19 +00:00
Bill Wendling
5c442aafb6 CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG
combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.

llvm-svn: 55579
2008-08-31 02:32:12 +00:00
Bill Wendling
4a9ded80e2 Cosmetic changes to Machine LICM. No functionality change.
llvm-svn: 55578
2008-08-31 02:30:23 +00:00