Reid Spencer
fa12fdc543
Revert last changes as they introduced other problems.
...
llvm-svn: 35115
2007-03-15 03:25:34 +00:00
Evan Cheng
1464c63d5d
ARM isel should match ldr x +/- x * (2^n) to ldr [x, +/- x, lsl #log2(n)].
...
llvm-svn: 35114
2007-03-14 23:26:40 +00:00
Reid Spencer
ce9e3ade3a
Regenerate.
...
llvm-svn: 35113
2007-03-14 23:13:06 +00:00
Reid Spencer
04cb556bca
The sign information was not propagating into the rename map so only the
...
last entry stored in the map could be retrieved for a given integer type.
Propagating the sign information required an invasive change to ensure that
all ValueRef (ValID) instances get the right sign information as well. Also,
put in some assertions to ensure the RenameMap always gives us out the type
that is expected.
This fixes PR1256 and
test/Assembler/2007-03-14-UgpradeLocalSignless.ll
llvm-svn: 35112
2007-03-14 23:11:45 +00:00
Reid Spencer
bf9ab59940
For PR1256:
...
Carry sign with ValID and make TypeInfo sortable (useful in a map).
llvm-svn: 35111
2007-03-14 23:08:04 +00:00
Reid Spencer
a8d6ff8dc9
Test case for PR1256.
...
llvm-svn: 35110
2007-03-14 23:07:24 +00:00
Evan Cheng
dc6ba035bc
Estimate a cost using the possible number of scratch registers required and use
...
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.
llvm-svn: 35109
2007-03-14 22:43:40 +00:00
Evan Cheng
00edaa08b5
Under X86-64 large code model, do not emit 32-bit pc relative calls.
...
llvm-svn: 35108
2007-03-14 22:11:11 +00:00
Evan Cheng
fc80b5b712
Notes about codegen issues.
...
llvm-svn: 35107
2007-03-14 21:03:53 +00:00
Duncan Sands
b3cbeb6a4a
Test that the size of a view converted object is determined by the target
...
type, not the source type.
llvm-svn: 35106
2007-03-14 20:24:53 +00:00
Evan Cheng
50a0af3b57
Clean up.
...
llvm-svn: 35105
2007-03-14 20:20:19 +00:00
Evan Cheng
2617c8dd3a
Oops.
...
llvm-svn: 35104
2007-03-14 19:44:58 +00:00
Jim Laskey
cfed9526c1
Change e-mail address.
...
llvm-svn: 35103
2007-03-14 19:32:21 +00:00
Jim Laskey
f19a75ee27
Add link to exception handling.
...
llvm-svn: 35102
2007-03-14 19:31:19 +00:00
Jim Laskey
fd20d94dda
Adding credit for PPC changes.
...
llvm-svn: 35101
2007-03-14 19:30:33 +00:00
Jim Laskey
9d1939dc2d
First draft of exception handling doc.
...
llvm-svn: 35100
2007-03-14 19:29:42 +00:00
Jeff Cohen
c9e2aa16cb
Make older versions of bison happy.
...
llvm-svn: 35099
2007-03-14 15:27:17 +00:00
Jeff Cohen
b19ec59b5c
Fix for VS 2005 problem supplied by Morten Ofstad.
...
llvm-svn: 35098
2007-03-14 15:25:21 +00:00
Evan Cheng
371b8e8fa9
X86-64 JIT is in large code model. Need stubs for direct calls.
...
llvm-svn: 35097
2007-03-14 10:51:55 +00:00
Evan Cheng
1092e481ce
x86-64 JIT stub codegen.
...
llvm-svn: 35096
2007-03-14 10:48:08 +00:00
Evan Cheng
15de6714a4
Preliminary support for X86-64 JIT stub codegen.
...
llvm-svn: 35095
2007-03-14 10:44:30 +00:00
Zhou Sheng
5c6399dab7
ShiftAmt might equal to zero. Handle this situation.
...
llvm-svn: 35094
2007-03-14 09:07:33 +00:00
Zhou Sheng
4415c2647e
Enable KnownZero/One.clear().
...
llvm-svn: 35093
2007-03-14 03:21:24 +00:00
Evan Cheng
0fe7224a46
New test.
...
llvm-svn: 35091
2007-03-13 23:31:47 +00:00
Evan Cheng
64f09e6241
This got better.
...
llvm-svn: 35090
2007-03-13 23:26:41 +00:00
Evan Cheng
399f56eac2
Try schedule def + use closer whne Sethi-Ullman numbers are the same.
...
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4
Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2
This creates more short live intervals which work better with the register
allocator.
llvm-svn: 35089
2007-03-13 23:25:11 +00:00
Evan Cheng
7cbde8351a
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2 ]
...
llvm-svn: 35088
2007-03-13 21:05:54 +00:00
Evan Cheng
7b24b3e474
Zero is always a legal AM immediate.
...
llvm-svn: 35087
2007-03-13 20:37:59 +00:00
Evan Cheng
bd964bd8eb
Correct type info for isLegalAddressImmediate() check.
...
llvm-svn: 35086
2007-03-13 20:34:37 +00:00
Duncan Sands
c56601a219
Test support for arrays with non-zero first index.
...
llvm-svn: 35084
2007-03-13 15:12:35 +00:00
Nicolas Geoffray
9c77df75ea
Stack and register alignment of call arguments in the ELF ABI
...
llvm-svn: 35083
2007-03-13 15:02:46 +00:00
Chris Lattner
efc2339bd7
ifdef out some dead code.
...
Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll
llvm-svn: 35082
2007-03-13 14:27:42 +00:00
Chris Lattner
0f75a6cc7f
testcase for PR1244
...
llvm-svn: 35081
2007-03-13 14:25:35 +00:00
Zhou Sheng
7cf2811ab3
For expression like
...
"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().
llvm-svn: 35080
2007-03-13 06:40:59 +00:00
Zhou Sheng
dfcf9376bc
Add zextOrCopy() into APInt for convenience.
...
llvm-svn: 35079
2007-03-13 06:16:26 +00:00
Zhou Sheng
14cef9ec74
In APInt version ComputeMaskedBits():
...
1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
2. Make code more efficient.
llvm-svn: 35078
2007-03-13 02:23:10 +00:00
Evan Cheng
92712d4884
Implement getTargetLowering() or else LSR won't be using ARM specific hooks.
...
llvm-svn: 35077
2007-03-13 01:20:42 +00:00
Evan Cheng
b2a5499d86
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35076
2007-03-12 23:37:10 +00:00
Evan Cheng
7767159f08
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
...
llvm-svn: 35075
2007-03-12 23:30:29 +00:00
Evan Cheng
06d83c8fce
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35074
2007-03-12 23:29:01 +00:00
Evan Cheng
0eeb8b59eb
More flexible TargetLowering LSR hooks for testing whether an immediate is
...
a legal target address immediate or scale.
llvm-svn: 35073
2007-03-12 23:28:50 +00:00
Evan Cheng
1fcdd7e1e5
Use new TargetLowering addressing modes hooks.
...
llvm-svn: 35072
2007-03-12 23:27:37 +00:00
Evan Cheng
f132fa5bba
More flexible TargetLowering LSR hooks for testing whether an immediate is
...
a legal target address immediate or scale.
llvm-svn: 35071
2007-03-12 23:26:27 +00:00
Evan Cheng
4224fa3617
Stupid bug: SSE2 supports v2i64 add / sub.
...
llvm-svn: 35070
2007-03-12 22:58:52 +00:00
Reid Spencer
7be576b4b0
Revert the last patch as it violates the conditions of sext/zext.
...
llvm-svn: 35068
2007-03-12 18:37:25 +00:00
Jeff Cohen
4e667fd766
Unbreak C++ build.
...
llvm-svn: 35067
2007-03-12 17:57:00 +00:00
Jeff Cohen
91930bc4d4
Unbreak VC++ build. Do not use identifiers starting with _ as they are reserved and
...
can collide with system defined names. Windows defines _BB, for example.
llvm-svn: 35066
2007-03-12 17:56:27 +00:00
Zhou Sheng
0145067d85
For APInt::z/sext(width), if width == BitWidth, just return *this.
...
llvm-svn: 35065
2007-03-12 17:47:45 +00:00
Reid Spencer
d59425085f
Add an APInt version of SimplifyDemandedBits.
...
Patch by Zhou Sheng.
llvm-svn: 35064
2007-03-12 17:25:59 +00:00
Reid Spencer
b18f916bbe
Add an APInt version of ShrinkDemandedConstant.
...
Patch by Zhou Sheng.
llvm-svn: 35063
2007-03-12 17:15:10 +00:00