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4 Commits

Author SHA1 Message Date
Matt Arsenault
c485a8dc2b AMDGPU: Fix ctlz combine for sub 32-bit types 
llvm-svn: 257353
 2016-01-11 17:02:06 +00:00
Matt Arsenault
b88ff2e112 AMDGPU: Pattern match ffbh pattern to instruction. 
The hardware instruction's output on 0 is -1 rather than 32.
Eliminate a test and select to -1. This removes an extra instruction
from the compatability function with HSAIL's firstbit instruction.

llvm-svn: 257352
 2016-01-11 17:02:00 +00:00
Matt Arsenault
9caa943926 AMDGPU: Custom lower i64 ctlz 
llvm-svn: 257348
 2016-01-11 16:50:29 +00:00
Matt Arsenault
c04b46aa04 LegalizeDAG: Expand ctlz with ctlz_zero_undef if legal 
llvm-svn: 257345
 2016-01-11 16:37:46 +00:00