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fac8748ca7
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115 Commits

Author SHA1 Message Date
Chris Lattner
fac8748ca7 use simplified operand addition methods. 
llvm-svn: 45437
 2007-12-30 01:01:54 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng
fdd03d0589 Doh 
llvm-svn: 44694
 2007-12-08 01:01:07 +00:00
Evan Cheng
28c2b7e647 Fix a compilation warning. 
llvm-svn: 44692
 2007-12-08 01:00:31 +00:00
Evan Cheng
8464a0bf00 Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether 
the stored register is killed.

llvm-svn: 44600
 2007-12-05 03:14:33 +00:00
Evan Cheng
58b387dfb0 Remove redundant foldMemoryOperand variants and other code clean up. 
llvm-svn: 44517
 2007-12-02 08:30:39 +00:00
Dale Johannesen
5fd9e7a615 Add parameter to getDwarfRegNum to permit targets 
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.

llvm-svn: 44056
 2007-11-13 19:13:01 +00:00
Bill Wendling
cc75435ebf Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack 
adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in
the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If
not, then there is the potential for the stack to be changed while the stack's
being used by another instruction (like a call).

This can only result in tears...

llvm-svn: 44037
 2007-11-13 00:44:25 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
 2007-11-11 19:50:10 +00:00
Evan Cheng
0449186690 - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. 
- Fix some copy+paste bugs.

llvm-svn: 43153
 2007-10-18 22:40:57 +00:00
Evan Cheng
c852780685 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. 
llvm-svn: 43150
 2007-10-18 21:29:24 +00:00
Evan Cheng
f536e2f41e - Added a few target hooks to generate load / store instructions from / to any 
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621
 2007-10-05 01:32:41 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!

llvm-svn: 42346
 2007-09-26 06:25:56 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng
45eb268032 Only adjust esp around calls in presence of alloca. 
llvm-svn: 40030
 2007-07-19 00:42:58 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Evan Cheng
4af116139b Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37894
 2007-07-05 07:11:03 +00:00
Evan Cheng
ff31eed2be Add missing const qualifiers. 
llvm-svn: 37342
 2007-05-29 18:42:18 +00:00
Evan Cheng
9f0ffdf4b3 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Lauro Ramos Venancio
4f648c68cd Fix PR1390 in a better way. 
llvm-svn: 36916
 2007-05-07 23:15:16 +00:00
Lauro Ramos Venancio
236cf4a51b Fix PR1390. 
Don't spill extra register to align the stack.

llvm-svn: 36814
 2007-05-05 23:44:41 +00:00
Lauro Ramos Venancio
1d84c031a0 Debug support for arm-linux. 
Patch by Raul Herbster.

llvm-svn: 36690
 2007-05-03 20:28:35 +00:00
Evan Cheng
e47ec4d104 eliminateFrameIndex() change. 
llvm-svn: 36626
 2007-05-01 09:13:03 +00:00
Evan Cheng
248de25fb5 Under normal circumstances, when a frame pointer is not required, we reserve 
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.

llvm-svn: 36607
 2007-05-01 00:52:08 +00:00
Lauro Ramos Venancio
54544c8835 add parenthesis. 
llvm-svn: 36514
 2007-04-27 20:10:08 +00:00
Lauro Ramos Venancio
f9641d332a In Thumb mode, the frame register must be R7. 
llvm-svn: 36512
 2007-04-27 17:58:03 +00:00
Evan Cheng
7f44e880dc Match MachineFunction::UsedPhysRegs changes. 
llvm-svn: 36452
 2007-04-25 22:13:27 +00:00
Lauro Ramos Venancio
5e0a3ef555 Fix a bug in getFrameRegister. 
Reported by Raul Herbster.

llvm-svn: 36262
 2007-04-19 14:09:38 +00:00
Anton Korobeynikov
f3e62a428a Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.

llvm-svn: 36146
 2007-04-16 18:10:23 +00:00
Evan Cheng
db15aa24f9 Fixed a bug that causes codegen of noop like add r0, r0, #0. 
llvm-svn: 35627
 2007-04-03 21:31:21 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng
9839628fd1 Fix one more Thumb eliminateFrameIndex bug. 
llvm-svn: 34990
 2007-03-07 00:12:18 +00:00
Evan Cheng
63ffd3e17f Register scavenging is now on by default for ARM. 
llvm-svn: 34987
 2007-03-06 22:02:53 +00:00
Evan Cheng
7c90fb2d67 Scavenge a register using the register scavenger when needed. 
llvm-svn: 34966
 2007-03-06 10:03:56 +00:00
Dale Johannesen
a6003a9eb6 eliminate unnecessary reset of SP in epilog on darwin 
llvm-svn: 34824
 2007-03-02 01:17:17 +00:00
Evan Cheng
07dcde8ba2 Use a spilled free callee-saved register as scratch register. 
llvm-svn: 34785
 2007-03-01 08:57:52 +00:00
Evan Cheng
8d3d4155e5 - Track which callee-saved registers are spilled. 
- Some code clean up.

llvm-svn: 34783
 2007-03-01 08:26:31 +00:00
Evan Cheng
5dc0ece7cb Doh. ARM::PC is obvious a reserved register. 
llvm-svn: 34763
 2007-02-28 23:12:34 +00:00
Evan Cheng
db591ecaa8 Make requiresRegisterScavenging determination on a per MachineFunction basis. 
llvm-svn: 34711
 2007-02-28 00:59:19 +00:00
Evan Cheng
fa23d8e51f Start making use of RegScavenger. 
llvm-svn: 34708
 2007-02-28 00:21:58 +00:00
Evan Cheng
a19dd6f388 Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve register kill info. 
llvm-svn: 34692
 2007-02-27 21:12:35 +00:00
Lauro Ramos Venancio
19040a3f0d bugfix: SP wasn't updated for varargs when frame pointer was eliminated. 
llvm-svn: 34537
 2007-02-23 21:53:48 +00:00
Evan Cheng
bd3219f5bf Add option to turn on register scavenger; By default, spills kills the register being stored. 
llvm-svn: 34514
 2007-02-23 01:09:11 +00:00
Jim Laskey
6a937ad320 Support to provide exception and selector registers. 
llvm-svn: 34482
 2007-02-21 22:54:50 +00:00
Evan Cheng
e4ab9c032b Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. 
llvm-svn: 34428
 2007-02-19 21:49:54 +00:00
Reid Spencer
b27fcf3482 For PR1207: 
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.

llvm-svn: 34399
 2007-02-19 03:20:00 +00:00
Evan Cheng
8c2508f1ac Added getReservedRegs(). 
llvm-svn: 34376
 2007-02-17 11:06:00 +00:00
Evan Cheng
dc15bc54a4 isLowRegister() expects input is a physical register. 
llvm-svn: 34013
 2007-02-07 21:44:33 +00:00